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Staying On the Path to Moore’s Law Requires 3D Integration

As the semiconductor industry struggles to maintain its momentum down the path of Moore’s Law, it is becoming clear that in addition to scaling line widths and chip sizes downward, some form of 3D IC integration will be necessary to achieve the interconnection density, manufacturing yields and cost targets.

By vertically stacking and interconnecting semiconductor layers (3D integration), as opposed to continuing to shrink line widths, chip designers have the potential to get around the limitations of geometric scaling; enable a significant increase in performance and reduction in power consumption through reduced signal paths; and achieve true cost reduction through the use of proven fabrication techniques that will increase yields.

The crucial processing technology elements for 3D IC integration include: 1) through silicon via (TSV) formation; 2) wafer thinning; and 3) scalable wafer-level bonding technologies with 3D interconnect for W2W (wafer-to-wafer) or D2W (die-to-wafer) fabrication processes. The semiconductor manufacturers who adopt the optimum combination of these technologies will be the ones who lead the industry to the next level of higher device performance and lower fabrication costs.

Read the entire article by Ziptronics, Inc. on SOCcentral.

What, Why and How of Through-Silicon Vias Featured

Through-silicon vias (TSVs) are not exactly new. In fact, some mobile phones in Japan already contain TSVs, and there are also military and medical applications in commercial production. However, until 45nm, interest in TSVs was less common. But, with advances in 32/28- and 22-nm technology somewhat slowed by technological issues, TSVs are beginning to emerge as a viable construct that will enable the industry to continue expanding the functionality of chips at 45nm and below.

So what exactly is a TSV, and why is it becoming a practical technology now? To answer that question, let’s take a quick look at chip-stacking technologies.

Read the entire article by Mentor Graphics Corp. on SOCcentral.

Test Standards Emerge to Improve 3D-Chip Yield

Some industry experts have been so bold as to assert that stacking multiple silicon die in a single package is the most effective way for the industry to continue along the trajectory of Moore’s law. This may or may not be true, but the fact remains that 3D chips with multiple stacked die are becoming critical to many types of electronic systems. Unfortunately, the yield on 3D chips can be surprisingly low because of the inadequacies of older chip-level validation and test technologies. Fortunately, several industry standards and advances by test companies are providing a glimmer of light at the end of the tunnel.

Read the entire article by ASSET InterTech, Inc. on SOCcentral.