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 Category: Special Topics: 3D ICs: Thursday, September 09, 2010
 3-D ICs

Featured Articles

Staying On the Path to Moore’s Law Requires 3D Integration

As the semiconductor industry struggles to maintain its momentum down the path of Moore’s Law, it is becoming clear that in addition to scaling line widths and chip sizes downward, some form of 3D IC integration will be necessary to achieve the interconnection density, manufacturing yields and cost targets.

By vertically stacking and interconnecting semiconductor layers (3D integration), as opposed to continuing to shrink line widths, chip designers have the potential to get around the limitations of geometric scaling; enable a significant increase in performance and reduction in power consumption through reduced signal paths; and achieve true cost reduction through the use of proven fabrication techniques that will increase yields.

The crucial processing technology elements for 3D IC integration include: 1) through silicon via (TSV) formation; 2) wafer thinning; and 3) scalable wafer-level bonding technologies with 3D interconnect for W2W (wafer-to-wafer) or D2W (die-to-wafer) fabrication processes. The semiconductor manufacturers who adopt the optimum combination of these technologies will be the ones who lead the industry to the next level of higher device performance and lower fabrication costs.

Read the entire article by Ziptronics, Inc. on SOCcentral.

What, Why and How of Through-Silicon Vias Featured

Through-silicon vias (TSVs) are not exactly new. In fact, some mobile phones in Japan already contain TSVs, and there are also military and medical applications in commercial production. However, until 45nm, interest in TSVs was less common. But, with advances in 32/28- and 22-nm technology somewhat slowed by technological issues, TSVs are beginning to emerge as a viable construct that will enable the industry to continue expanding the functionality of chips at 45nm and below.

So what exactly is a TSV, and why is it becoming a practical technology now? To answer that question, let’s take a quick look at chip-stacking technologies.

Read the entire article by Mentor Graphics Corp. on SOCcentral.

Test Standards Emerge to Improve 3D-Chip Yield

Some industry experts have been so bold as to assert that stacking multiple silicon die in a single package is the most effective way for the industry to continue along the trajectory of Moore’s law. This may or may not be true, but the fact remains that 3D chips with multiple stacked die are becoming critical to many types of electronic systems. Unfortunately, the yield on 3D chips can be surprisingly low because of the inadequacies of older chip-level validation and test technologies. Fortunately, several industry standards and advances by test companies are providing a glimmer of light at the end of the tunnel.

Read the entire article by ASSET InterTech, Inc. on SOCcentral.

3D IC Information Sources


3D-IC technology has become a very hot topic! It seems that every foundry, design house, and research group now has a 3D program. One of the most comrehensive sources — if not the most comprehensive source — for 3D IC products and services; 3D IC tools and equipment; 3D IC research; and market research, analysis, consulting, and reporting has been compiled by Tezzaron Semiconductor in its 3D IC Industry Summary.

The 3D-IC Alliance publishes a relatively current list of papers, articles, & blogs about 3D-ICs available from from a variety of online sources, most of which are free or do not require registration.



Designer's Mall

SOCcentral news items about 3D Integrated Circuits

Tabula Builds New Sales Rep Organization (7/16/2010)
CEA-Leti Building Complete 300-mm R&D Line Dedicated to 3D-Integration (7/12/2010)
EC Funds Green Cloud Services Project Investigating Use of ARM Architecture in Data Centers (6/21/2010)
Elpida, PTI, and UMC Partner on 3D IC Integration Development (6/21/2010)
CEA-Leti and DOCEA Power to Combine Expertise on 3D Integration, Thermal and Low-Power Design (6/17/2010)
E-System Design Announces New Breakthrough for 3D Interconnect Parasitic Extraction (6/17/2010)
Cadence Delivers TLM-Driven Design and Verification, 3D-IC Design and Integrated DFM Capabilities to TSMC Reference Flow 11.0 (6/14/2010)
Tabula’s CTO Steve Teig to Speak During DAC Luncheon (5/25/2010)
Tabula Launches ABAX Family of 3-D Programmable Logic Devices (3/16/2010)
Tier Logic Announces 3D-Based Technology for FPGAs and ASICs (3/11/2010)
IMEC and Synopsys Collaborate on 3D Stacked IC Development (3/10/2010)
Tabula Introduces Spacetime 3-D Programmable Logic Architecture (3/1/2010)
ALLVIA Integrates Embedded Capacitors for Silicon Interposers and 3D Stacked Semiconductors (2/25/2010)
Tanner EDA and Sound Design Technologies Announce PDK Collaboration for Thin Film Technologies (2/16/2010)
ALLVIA Completes Reliability Testing of Silicon Interposer for Stacked Semiconductors (1/13/2010)
Esterel Technologies and Quantum3D Form Strategic Alliance to Offer One-Stop Solution for Embedded Graphics Display Development (12/2/2009)
Ziptronix to License 3D IC Technology for Imaging Systems (11/19/2009)
Si2 Announces Sponsorship of "3D Architectures for Semiconductor Integration and Packaging Conference" (11/13/2009)

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Magazine & Journal articles on 3D Integrated Circuits

Setting a New Standard for Through-Silicon Via Reliability Electronic Design Magazine (10/19/2009)
What, Why and How of Through-Silicon Vias SOCcentral (10/6/2009)
Test Standards Emerge to Improve 3D-Chip Yield SOCcentral (10/5/2009)
Staying On the Path to Moore’s Law Requires 3D Integration SOCcentral (8/19/2009)
High-Density IC Packaging Looks at the Third Dimension Electronic Design Magazine (7/23/2009)
Packaging Goes Vertical Electronic Engineering Times (EE Times) (11/24/2008)
3-D Integration Lacking in Design and Test Support Semiconductor International (11/18/2008)
3D Chip-Package-Board Modeling Printed Circuit Design & Fab (11/4/2008)
What Are the Main Challenges to Successful IP Integration? Electronic Engineering Times (EE Times) (5/28/2002)

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Tutorials, White Papers & Conference Papers on 3D Integrated Circuits

A Thermally-Aware Performance Analysis of Vertically Integrated (3D) Processor-Memory Hierarchy Design Automation Conference (DAC)
CAD Implications of New Interconnect Technologies (32.4) Design Automation Conference (DAC)
Design Methodology for Wireless Nodes with Printed Antennas Design Automation Conference (DAC)
Exploring Compromises among Timing, Power and Temperature in Three-Dimensional Integrated Circuits Design Automation Conference (DAC)
Interconnects in the 3rd Dimension: Design and Process Challenges for 3D ICs (32.1) Design Automation Conference (DAC)
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors (34.4) Design Automation Conference (DAC)
Signature-Based Workload Estimation for Mobile 3D Graphics Design Automation Conference (DAC)

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