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Testing the 3D Waters There certainly has been no lack of talk these days on the industry's eventual migration to 3D-ICs. In fact, we already see a number of companies begin to test the 3D waters. But there are still a number of challenges to solve and technologies to develop or refine to fully enable this migration. These challenges include both design automation as well as wafer-equipment-related issues.... read more. By Stephen Pateras, Product Marketing Director, Mentor Graphics Corp.'s Silicon Test Products.

3D ICs with TSVs: Design Challenges and Requirements

As demands accelerate for increasing density, higher bandwidths, and lower power, many IC design teams are looking to 3D ICs with through-silicon vias (TSVs). 3D ICs promise "more-than-Moore" integration by packing a great deal of functionality into small form factors, while improving performance and reducing costs. 3D-IC packages may accommodate multiple heterogeneous die — such as logic, memory, analog, RF, and micro-electrical mechanical systems (MEMS) — at different process nodes, such as 28nm for high-speed logic and 130nm for analog. This provides an alternative to system-on-chip (SOC) integration, potentially postponing an expensive move to a new process node for all of the functionality developers want to place in a single package.

Read the entire article from Cadence Design Systems, Inc. on SOCcentral.

Power and Thermal Modeling and Analysis of Multi-Die Packages

Today's system designer has an unprecedented technology portfolio to conjure up the most-sophisticated, feature-rich designs for a variety of markets. But to produce designs that are competitive and meet or exceed customer expectations requires making trade-offs early and often between the power and performance, schedules and risks, and costs. The promise of multi-die stacked products is one technology to offer more features, earlier, in the smallest form factor. To fulfill that promise, the designer must harness complex, interactive modeling of the power and thermals associated with multiple die in a common package with a variety of process technology, interconnects and materials. Today's system engineer must match the right power and thermal management to the operating conditions to provide the best power, performance and cost.

Read the entire article from DOCEA Power on SOCcentral.

3D-IC System Verification Methodology: Solutions and Challenges

The performance and cost savings for moving toward through-silicon via (TSV)-based 3D integration motivations have been identified. 3D-IC technology enables shorter critical interconnections, which will reduce both the delays and power. In addition, it will allow easy reuse of IP blocks, heterogeneous technology integration, and a reduction of the form factor. Technological issues for 3D-IC technology include TSV formation, die thinning, thinned-die handling, assembling and testing. But the technology is at a stage that will allow for significant commercialization in the next few years.

Read the entire article from Mentor Graphics Corp. on SOCcentral.

Test Automation of 3D Integrated Systems

Advances in packaging technologies have led to the development of three-dimensional (3D) integrated systems that offer the potential to deliver significant improvements in performance, power, functional density, and form factor over systems that rely on standard packaging-integration techniques. Although the design and test requirements for these highly integrated systems are still evolving, it is evident that advanced test automation will be essential in ramping 3D systems to volume production.

Read the entire article from Synopsys, Inc. on SOCcentral.

Staying On the Path to Moore’s Law Requires 3D Integration

As the semiconductor industry struggles to maintain its momentum down the path of Moore's Law, it is becoming clear that in addition to scaling line widths and chip sizes downward, some form of 3D-IC integration will be necessary to achieve the interconnection density, manufacturing yields and cost targets. The crucial processing technology elements for 3D IC integration include: 1) through-silicon via (TSV) formation; 2) wafer thinning; and 3) scalable wafer-level bonding technologies with 3D interconnect for W2W (wafer-to-wafer) or D2W (die-to-wafer) fabrication processes. The semiconductor manufacturers who adopt the optimum combination of these technologies will be the ones who lead the industry to the next level of higher device performance and lower fabrication costs.

Read the entire article from Ziptronics, Inc. on SOCcentral.

What, Why and How of Through-Silicon Vias

Through-silicon vias (TSVs) are not exactly new. However, until 45nm, interest in TSVs was less common. But, with advances in 32/28- and 22-nm technology somewhat slowed by technological issues, TSVs are beginning to emerge as a viable construct that will enable the industry to continue expanding the functionality of chips at 45nm and below. So what exactly is a TSV, and why is it becoming a practical technology now? To answer that question, let's take a quick look at chip-stacking technologies.

Read the entire article from Mentor Graphics Corp. on SOCcentral.

Test Standards Emerge to Improve 3D-Chip Yield

Some industry experts have been so bold as to assert that stacking multiple silicon die in a single package is the most effective way for the industry to continue along the trajectory of Moore's law. This may or may not be true, but the fact remains that 3D chips with multiple stacked die are becoming critical to many types of electronic systems. Unfortunately, the yield on 3D chips can be surprisingly low because of the inadequacies of older chip-level validation and test technologies. Fortunately, several industry standards and advances by test companies are providing a glimmer of light at the end of the tunnel.

Read the entire article from ASSET InterTech, Inc. on SOCcentral.