Category: Special Topics: Timing Analysis & Closure:

Friday, May 24, 2013

Timing Analysis & Closure

Clock Domain Crossing Demystified

The increase in SOC designs is leading to the extensive use of asynchronous clock domains. The clock-domain-crossing (CDC) interfaces are required to follow strict design principles for reliable operation. Also, verification of proper CDC design is not possible using standard simulation and static timing-analysis (STA) techniques. As a result, CDC-verification tools have become essential in design flows. This article makes a fundamental observation that the inability to accomplish timing closure across the CDC interface is the root cause of the CDC problem. In addition, this article identifies practical considerations for effective CDC verification and recommends a hierarchical top-down, bottom-up methodology — with result inheritance and effective use of formal analysis — to minimize the manual engineering effort in CDC verification.

Read the entire article from Real Intent, Inc. on SOCcentral.

Accelerate Design Closure with Multicore Timing Analysis and Optimization

With the trend towards increasing IC design size and complexity showing no sign of slowing, the computing load required to complete projects on time is exploding. But, the growth in computing power is coming from multiple cores instead of higher clock speeds, which means IC implementation software must run efficiently on the latest multi-core hardware. Although some implementation tasks (e.g., placement and routing) have been parallelized to a certain extent, parallelizing the very core of the physical design system — the timing analysis and optimization engines — is the smart way to improve runtimes and maintain tight design schedules. Scalable, parallel timing analysis and optimization capabilities can dramatically cut overall design time.

Read the entire article from Mentor Graphics Corp. on SOCcentral.

Bridging SOC Architectures for Faster Timing Closure

The complexities of SOC timing closure are addressed in two fundamental ways today. The first is to continue to utilize new EDA tools in the design flow that improve simulation and analysis. A second way is to use architecture tools that help better predict behavior of key elements before the chip design begins, such as data flows and IP interoperability, to mitigate timing-closure risks before the chip is designed. Some companies today use both. But given the levels of extreme complexity now on a single chip, and analyzing the directions that both the EDA and IP providers are taking to support each of the methodologies highlighted briefly above, is it time to revisit the basic architectural philosophies used for SOCs? And how does this help the timing-closure problem?

Read the entire article from ChipStart on SOCcentral.

Probabilistic Timing Analysis

Because of shrinking feature sizes and the decreasing faithfulness of the manufacturing process to design features, process variation has been one of the constant themes of IC designers as new process nodes are introduced. This article reviews the problem and proposes a "probabilistic" approach as a solution to analysis and management of variability.

Read the entire article by Library Technologies, Inc. on SOCcentral.

Designer's Mall

SOCcentral news items about Timing Analysis & Closure

TSMC Certifies Cadence Tempus Timing Sign-off Solution for 20-nm Designs (5/22/2013)

Ausdia Receives Patent for System and Method for Automatically Managing Clock Relationships in IC Designs (5/20/2013)

Cadence Introduces the Tempus Timing Sign-off Solution (5/20/2013)

FishTail Design Automation Joins Cadence Connections Program (5/8/2013)

Symtavision Adds Ethernet Timing Analysis to SymTA/S (4/22/2013)

STARC Endorses FishTail for Automated Merging of Multi-Mode Design Constraints for Timing Sign-Off (4/3/2013)

Synopsys Speeds Timing Closure with Advanced Sign-Off-Driven ECO Guidance (3/25/2013)

Oasys Design Systems Expands into South Korea (2/27/2013)

EMA Releases TimingDesigner 9.3 with New Documentation Graphics and a Multi-Diagram Interface (2/20/2013)

HP Deploys Mentor Graphics' Questa CDC (12/17/2012)

SynaptiCAD's Timing Diagram Editors Simplify FPGA Synthesis (12/4/2012)

Open-Silicon Uses Synopsys IC Compiler to Achieve 1.3GHz on Quad-Core ARM Cortex-A9 MPCore Processor (10/2/2012)

Fujitsu Semiconductor Selects Cadence Sign-Off Solution for Its Newest Reference Design Flow (7/17/2012)

Synopsys and Samsung Deliver a Complete Solution for 20-nm Node (6/4/2012)

Timing Closure Experts Launch New Company, Announce Proven Timing Constraints Platform (6/4/2012)

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Magazine & Journal articles on Timing Analysis & Closure

The Efficient Implementation of Asynchronous Logic in COTS FPGAs EE Times Programmable Logic Designline (1/4/2013)

20-nm Timing Analysis: A Practical and Scalable Approach Tech Design Forum (12/6/2012)

Blindsided by a Glitch SOCcentral (11/19/2012)

Removing Pessimism and Optimism in Timing Analysis EE Times EDA Designline (10/1/2012)

Resolving Timing Mis-Correlation Using Timing Uncertainties EDN Magazine (7/19/2012)

Understanding Clock Jitter and How to Improve It EE Times RF & Microwave Designline (7/17/2012)

Software Extends Hardware-in-the-Loop Real-Time Simulation EE Times Automotive Designline (6/25/2012)

Applications and Use of Stage-Based OCV EE Times EDA Designline (5/21/2012)

Introduction to Multisource Clock Tree Systems Electronic Design Magazine (2/10/2012)

Reducing Sign-Off Corners to Achieve Faster 40-nm SOC Design Closure EE Times Embedded (12/20/2011)

Dealing with Multi-Vt and Multi-Voltage Domain Timing/ Temperature Inversion Challenges EE Times Embedded (12/7/2011)

Reducing Turnaround Time with Hierarchical Timing Analysis EE Times EDA Designline (10/3/2011)

Latches and Timing Closure: A Mixed Bag EDN Magazine (9/22/2011)

Latches and Timing Closure: A Mixed Bag EE Times EDA Designline (8/2/2011)

Selecting Clock Skews at Advanced Nodes EE Times EDA Designline (7/25/2011)

Meeting Timing Specs on Boards with Picoseconds of Margin EE Times Signal Processing DesignLine (1/19/2011)

Critical False-Path Analysis Through Sensitization Methods EDN Magazine (12/29/2010)

Choosing an Effective Embedded SOC ASIC Design Strategy EE Times Embedded (12/13/2010)

How to Achieve Timing Closure In Large, Complex FPGA Designs EE Times Programmable Logic Designline (9/21/2010)

Web-Based IC Customization Revolutionizes Timing Circuits Electronic Products Magazine (7/1/2010)

Path-Specific Derating to Reduce Timing Pessimism EDN Magazine (6/25/2010)

Timing Closure On FPGAs EE Times Programmable Logic Designline (4/22/2010)

An Easy Way to Adopt Statistical Timing Analysis and Do Better Designs SOCcentral (1/21/2010)

Accelerate Design Closure with Multi-Core Timing Analysis and Optimization SOCcentral (11/2/2009)

Probabilistic Timing Analysis SOCcentral (10/31/2009)

Calculating Corner Independent Timing Closure EE Times Embedded (10/30/2009)

Establishing Timing Correlation Between Tools EDN Magazine (3/19/2009)

Statistical Static Timing Analysis: A Better Alternative EE Times EDA Designline (2/3/2009)

Test Structures Make Designs Harder to Verify SOCcentral (10/28/2008)

Preserving the Intent of Timing Constraints EE Times EDA Designline (5/17/2008)

Statistical Timing Gets a Foothold in Leading-edge Designs EDN Magazine (3/24/2008)

Trip Points for IC Timing Analysis EDN Magazine (3/20/2008)

Understanding Clock Domain Crossing Issues EE Times EDA Designline (12/24/2007)

Process Intelligent Modeling and Statistical STA improve DFM EE Times EDA Designline (9/11/2007)

Statistical Timing Analysis: Sign-off for a New Generation SOCcentral (7/19/2007)

Simultaneous Multi-Scenario Timing Optimization for High-Performance Digital IC Designs SOCcentral (7/12/2007)

Timing Constraints Generation Technology EE Times EDA Designline (5/17/2007)

Timing Is Everything in SOC Design EDN Magazine (1/4/2007)

Practical Applications of Statistical Static Timing Analysis EE Times EDA Designline (12/18/2006)

Cell Model Creation for Statistical Timing Analysis eeDesign (EE Times EDA News) (7/3/2006)

Evaluate IP Timing Constraints Before Use in SOC Designs SOCcentral (7/1/2006)

On-Chip Variation and Timing Closure EDN Magazine (6/22/2006)

Timing Analysis Rounds the Corner to Statistics Electronic Design Magazine (12/15/2005)

Reducing False Errors in Clock-Domain Crossing Analysis eeDesign (EE Times EDA News) (1/17/2005)

Analysis of Board Layout Helps Cure Jitter Problems EDN Magazine (8/5/2004)

FPGAs Go, Go, Go: Solving the FPGA Timing Closure Challenge for High-Speed Designs Chip Design Magazine (7/1/2004)

Tackling Multiple Clocks in SoCs Electronic Engineering Times (EE Times) (3/17/2004)

It Takes a Super Sleuth to Really Debug Clock-Timing Problems Electronic Design Magazine (2/16/2004)

Non-Linear Effects in Low-Power Sub-100nm Designs Electronic Engineering Times (EE Times) (1/15/2004)

Using RTL Floorplanning to Budget Nanometer Designs Electronic Engineering Times (EE Times) (1/15/2004)

"Best practices" Improve Hierarchical Design Constraints eeDesign (EE Times EDA News) (12/1/2003)

Skew Generation and Analysis in Timing-Critical Circuits EDN Magazine (11/13/2003)

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Tutorials, White Papers & Conference Papers on Timing Analysis & Closure

Beyond DDR: Signal Integrity and Timing Analysis of Quad Band Memory (QBM) Systems Signal Integrity Software, Inc. (SiSoft)

Clock Concurrent Optimization Azuro, Inc.

Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification Atrenta, Inc.

High-Speed Design Challenges for a 1.4GHz Network Processor Signal Integrity Software, Inc. (SiSoft)

Hybrid Timing Analysis Nassda Corp.

Meeting Timing Budgets for DDR Memory Interfaces Synopsys, Inc.

Nanometer Analysis Improves Timing Accuracy in Synthesis-Driven Flows Nassda Corp.

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