| Critical False-Path Analysis Through Sensitization Methods by Freescale Semiconductor, Inc. in EDN Magazine |
December 29, 2010 -- Static and dynamic false-path determination is essential for accurate application of false paths in an SOC design. In an SOC-design flow, it is very important to apply correct and appropriate timing constraints to the design ... read more |
| Allocating Dynamic Memory with Confidence by EE Times Memory Designline |
December 27, 2010 -- Embedded software applications face many challenges that are not present on desktop computers. A device with a dedicated function is not generally regarded as a computer, even if a significant part of it is software. Users w ... read more |
| Understanding the Basics of PLL Frequency Synthesis by Cypress Semiconductor Corp. in EE Times Planet Analog |
December 23, 2010 -- Configuring a phase locked loop (PLL) for a given frequency-synthesis application can simultaneously be both a quick-and-easy process as well as a time-consuming, tedious, and iterative process. This dual nature in PLL syste ... read more |
| FMEA Eases Automotive ASIC Design and Deployment by ZMD AG in EE Times Automotive Designline |
December 22, 2010 -- All product development includes an assessment of performance, quality and reliability before a product reaches market. This is especially true in the automotive industry, where manufacturers offer warrantees/ guarantees bas ... read more |
| The War Is Over: C++ and SystemC Coexist In a Single Flow by Mentor Graphics Corp. in EE Times EDA Designline |
December 15, 2010 -- Since its debut in 2004, the current generation of high-level synthesis (HLS) tools has made tremendous progress in terms of both quality of results (QoR) and wider applicability. The success of this technology cannot be den ... read more |
| Multiphysics Simulation Enhances Electronics System Design by EDN Magazine |
December 15, 2010 -- Simulation of electronic circuits and systems has long focused on the analysis of electrical signals: voltage or current waveforms for analog engineers and binary bit patterns for digital engineers. Now that IC density has g ... read more |
| Automating Rule Sets for Safety-Critical HDL Coding by Mentor Graphics Corp. in Electronic Engineering Times (EE Times) |
December 14, 2010 -- During the development process for safety-critical designs, all precautions should be taken to prevent device failures from all foreseeable sources, including those due to poor design methods and processes. Poor process, suc ... read more |
| Validate Hardware/ Software for Nextgen Mobile/ Consumer Apps Using System Development Tools by Cadence Design Systems, Inc. in EE Times Embedded |
December 14, 2010 -- A new breed of mobile smartphone platforms and sophisticated embedded consumer devices is now emerging requiring applications software and extensions that go far beyond just enabling user-level software customization. The de ... read more |
| Choosing an Effective Embedded SOC ASIC Design Strategy by Freescale Semiconductor, Inc. in EE Times Embedded |
December 13, 2010 -- In large and complex system-on-chip ASIC design, two of the most challenging tasks are those involving design closure, timing routing and power. It is a tedious task to converge on timing and routing, owing to the limitation ... read more |
| Using Mixed-Signal FPGAs to Take Motion Control to the Next Step by Microsemi Corp. in EE Times Programmable Logic Designline |
December 12, 2010 -- Motion-control systems (and by extension, motor-control methods) are becoming more complex as they address ever-escalating market needs. Increasing demands for energy efficiency, increased functionality, reduced size, and hi ... read more |
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