Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2010: Saturday, May 18, 2013
How to Make Virtual Prototyping Better than Designing with Hardware: Part 1 - Use Cases for Virtual Prototyping  
Publication: EE Times Embedded
 Printer friendly
 E-Mail Item URL

June 22, 2010 -- Engineers embrace model-based design in many different disciplines associated with product development, for example, finite element analysis in mechanical engineering and circuit simulation for electrical engineering. Modeling enables development before physical prototypes are available. It enables development that is not possible, or is very difficult, with the physical or actual product. Virtual prototyping of embedded hardware brings the model-based design paradigm to embedded system development.

The use of virtual prototypes prior to hardware delivery has well-documented benefits for architectural exploration, early software development, golden reference specifications, reduced silicon turns, and software/hardware co-verification. This article focuses on the virtual prototype benefits after physical prototype availability. The Google Android Emulator is a well-known example of how a VP delivers value even after silicon is available .

By Everett Lumpkin and Casey Alford. (Lumpkin is Senior Function Design Methodology and Automation Engineer with Delphi Corp. and Alford is the Director, Field Engineering & Technical Services with Embedded Systems Technology.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Embedded website.

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, virtual prototyping, EE Times Embedded,
596/31687 6/22/2010 1806 188


Designer's Mall
0.15625



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.596  0.234375