Publication: EE Times Embedded
Contributor: Cadence Design Systems, Inc.
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August 9, 2010 -- In the past, most of the design effort in an SOC was centered on creating unique new logic that differentiated the design from other designs available. It has been this understanding of SoC design that drove the evolution of design tools and technologies over the past decade – the focus on new logic creation. Fast-forward to today and we find a very different situation, with SOCs that contain large amounts of internal and third-party intellectual property (IP) integrated into complex systems.
With this change, much of the design effort is now spent on integration, verification, and software development, with little in the way of tools and technologies to automate this integration.
By Neil Hand. (Neil Hand is Group Director, Product Marketing at Cadence Design Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Embedded website.
Read more about
Cadence Design Systems, Inc.
on SOCcentral.com |
| | Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, Cadence Design Systems, EE Times Embedded,
| | 596/31987 8/16/2010 2644 247 | |
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