Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2010: Thursday, May 23, 2013
Harness Speed, Performance, Signal Integrity, and Low-Current Advantages of 65-nm QDR SRAMs  
Publication: EE Times Communications Designline
Contributor: Cypress Semiconductor Corp.
 Printer friendly
 E-Mail Item URL

August 23, 2010 -- There is increased demand for SRAMs with faster speed, better performance, lower currents, and better signal integrity for next-generation networking applications. To keep up with this demand, the 65-nm technology QDR families of devices have been introduced which offer significant advantages over 90-nm technology-based QDR devices. This article describes in detail the advantages of the 65-nm technology QDR family devices over their 90-nm technology equivalent and provides guidelines for simplifying the migration from 90-nm to 65-nm technology.

By Jayasree Nayar. (Nayar is a Senior Applications Engineer working in Cypress Semiconductor Corp.'s Memory and Imaging Division.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Communications Designline website.

Read more about
Cypress Semiconductor Corp.
on SOCcentral.com

Keywords: embedded systems, embedded system design, embedded memory, QDR SRAMs, EE Times Communications Designline, Cypress Semiconductor,
596/32030 8/23/2010 703 80


Designer's Mall
0.15625



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.596  0.21875