September 16, 2010 -- Performance verification of system bus fabrics is an increasingly complex problem. The bus fabrics themselves are growing in complexity, and an exact performance model of the entire bus fabric may not be available for reference. Performance bugs are often architectural in nature and, therefore, very difficult to fix. As a result, it is necessary to find a way to accurately validate the performance of complex bug fabrics early in the design flow.
VMM Performance Analyzer offers tools to make performance validation of bus systems easier. This application provides a flexible mechanism for capturing arbitrary user-defined performance data and saving it to an SQL database for subsequent analysis. In effect, it allows us to both select the important performance characteristics of our system and then gather performance results from large numbers of transfers through that system.
This article describes how we used the VMM Performance Analyzer to complete performance validation for an AXI bus arbiter. We begin with an overview of the Device Under Test and its existing VMM functional testbench. Next, we discuss the capabilities of VMM Performance Analyzer and show how it was added to the testbench. Then, we show how we collected and analyzed the resulting performance data. Finally, we conclude by summarizing our results and discussing future work using this methodology.
By Kelly Larson, John Dickol and Kari O'Brien. (Larson is verification manager, Dickol is design verification engineer, and O'Brien is SOC Architect at MediaTek Wireless, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.