Publication: EE Times Memory Designline
Contributor: Rambus, Inc.
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October 11, 2010 -- In a first set of simulations, the impact of Inter Signal Interference (ISI) and crosstalk on the eye opening of the data channel was investigated. For the ISI simulation, only the victim signal is transmitting while all other signals are kept quiet. For crosstalk simulations, all signals are transmitting data, however, the data pattern transmitted by the aggressor lines is different from the data transmitted on the victim line. All simulations use an ideal power supply for the transmitter and the receiver of the interface system. In order to achieve the best possible performance in this system, a nearly optimal PCB routing was assumed with minimum crosstalk. PCB signals were routed as striplines with a large spacing of 3w (three times the width of the signal line itself) between adjacent lines.
By Ralf Schmitt, Joong-Ho Kim, June Feng, Dan Oh, and Chuck Yuan. (All are with Rambus, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Memory Designline website.
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| | Keywords: ASICs, ASIC design, PCB design, 3D ICs, 3D chips, stacked ICs, packages, packaging, power integrity, signal integrity, noise, EE Times Memory Designline, Rambus,
| | 596/32441 10/25/2010 1096 142 | |
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