| Low-Cost Solution for Microcontroller In-System Power-Up Behaviour Evaluation by Infineon Technologies AG in Design & Reuse |
December 9, 2010 -- This article discusses a low cost, portable, reusable platform established to ease the in-system power-up behaviour evaluation of an MCU. This flexible platform is able to generate ramp-up signals at different speeds, startin ... read more |
| Dynamic Memory Allocation and Fragmentation In C and C++ by Mentor Graphics Corp. in Design & Reuse |
December 9, 2010 -- In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. However, the handling of such dynam ... read more |
| Building FPGA-Based Digital Downconverters With Graphical Design Tools by National Instruments Corp. in EE Times Programmable Logic Designline |
December 8, 2010 -- High-bandwidth digital downconverters (DDCs) are critical components in many high-performance systems, including receivers of modulated communications, medical imaging devices, and low-level RF control hardware for scientific ... read more |
| Analog Design Quality Closure: What's Missing from Current Flows? by Satin Technologies in EE Times EDA Designline |
December 6, 2010 -- The design of AMS circuits requires the adoption of specific recipes, the sharing of past experiences, and a huge number of design explorations with different constraints and parameters. The quality of results and the time to ... read more |
| Tips About Printed Circuit Board Design: Part 1 - Dealing With Harmful PCB Effects by EE Times Embedded |
December 6, 2010 -- Printed circuit boards (PCBs) are by far the most common method of assembling modern electronic circuits. Composed of a sandwich of insulating layer (or layers) and one or more copper conductor patterns, they can introduce va ... read more |
| Why Modems Are Going Soft by EDN Magazine |
December 6, 2010 -- Cellular communication has evolved at an enormous rate in terms of both features and performance. From the inception of GSM, through multiband, GPRS, EDGE, and onto 3G UMTS, the silicon technology and design methodologies hav ... read more |
| Use GPUs to Boost Acceleration by EDN Magazine |
December 2, 2010 -- In desktop, laptop, and notebook computing, multicore is now mainstream; single-core processors that pushed for higher and higher clock speeds long ago reached the point of diminishing returns, and today's baseline PC now typ ... read more |
| SOC-PLL Design Requires Trade-Offs by Silicon Creations in EDN Magazine |
December 2, 2010 -- PLLs (phase-locked loops) are common analog circuits in SOCs (systems-on-chip). Almost all SOCs with a clock rate greater than 30MHz use a PLL for frequency synthesis. However, a "one-size-fits-all" PLL does not exist. The de ... read more |
| Programmable ICs: The Next Innovation Engine by EE Times Programmable Logic Designline |
December 2, 2010 -- Semiconductor programmable ICs, led by FPGA devices, became immensely successful in recent years, their expanded performance and capabilities match all but the most advanced ASICs and ASSPs. The potential of programmable ICs ... read more |
| ABQ: Assertion Based Qualifier Methodology for Pre-Existing Environments by Samsung Electronics Co. Ltd. in Design & Reuse |
December 2, 2010 -- In the present verification scenario with shortening time-to-market, reuse of pre-existing verification environments becomes very important. It becomes part of verification engineer's scheduled work list to check on the quali ... read more |
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