| Using Requirements Planning In Embedded Systems Design: Part 3 - Defining System Timing Requirements by Microchip Technology, Inc. in EE Times Industrial Control Designline |
August 23, 2010 -- While the topic of timing has already been raised in previous parts in this series, the discussion here will be expanded to include the execution and response time of the software functions.
When discussing t ... read more |
| Using Requirements Planning In Embedded Systems Design: Part 2 - Extracting Communications Pathway Requirements by Microchip Technology, Inc. in EE Times Industrial Control Designline |
August 21, 2010 -- The next area of information to extract from the requirements document relates to communication pathways, both within the system and between the system and any external systems — specifically, information concerning the volume ... read more |
| Using Requirements Planning In Embedded Systems Design: Part 1 - Dissecting the Requirements Document by Microchip Technology, Inc. in EE Times Industrial Control Designline |
August 19, 2010 -- To begin any embedded system-level design, the developer needs a clear understanding of what the final software design must accomplish. The source of this information is the system requirements document, or simply the requirem ... read more |
| PCB Layout Techniques to Maximize Power Module Performance by National Semiconductor Corp. in EE Times Power Management Designline |
August 22, 2010 -- A new class of easy-to-use power modules offers an alternative to complex power designs and the printed circuit board (PCB) layout issues typically related to DC-DC converters. Nonetheless, there is still some engineering to b ... read more |
| The Future of SoC Verification: Enterprise Computing? by Electronic Engineering Times (EE Times) |
August 26, 2010 -- Perhaps the world of SOC verification gives the appearance of gradual and organized development. But the real story, as it emerges from an interview last week with Mentor Graphics DVT Division general manager John Lenyo, looks ... read more |
| SystemVerilog Configurable Coverage Model In an OVM setup: Concept of Reusability by AppliedMicro Corp. (AMCC) in EE Times EDA Designline |
August 24, 2010 -- With the advent of a new era in verification technology based on an advanced HVL like SystemVerilog, the concept of random-stimulus-based verification was born to verify today’s multi-million gate designs. In concept, every ve ... read more |
| Reusable Device Simulation Models for Embedded System Virtual Platforms by Mentor Graphics Corp. in Design & Reuse |
August 24, 2010 -- As embedded systems hardware becomes more powerful, the demand for high quality, sophisticated and compelling applications is increasing. This has led to the majority of embedded application developers to reusable legacy softw ... read more |
| Harness Speed, Performance, Signal Integrity, and Low-Current Advantages of 65-nm QDR SRAMs by Cypress Semiconductor Corp. in EE Times Communications Designline |
August 23, 2010 -- There is increased demand for SRAMs with faster speed, better performance, lower currents, and better signal integrity for next-generation networking applications. To keep up with this demand, the 65-nm technology QDR families ... read more |
| Dual-Core Architectures In Automotive SoCs by Freescale Semiconductor, Inc. in EE Times Automotive Designline |
August 23, 2010 -- High end automotives produced these days provide features like electronic stability control (ESC), traction control system (TCS), advanced driver assistance systems (ADAS) etc. These features require complex SOCs at heart whic ... read more |
| Using Switched Capacitors to Create Programmable Analog Logic Blocks In Mixed-Signal Designs by Cypress Semiconductor Corp. in EE Times Programmable Logic Designline |
August 18, 2010 -- Any physical system design needs both analog and digital functionality. Achieving a modular, programmable design is crucial for the demanding applications of future, which has led to more and more designs integrating subsystem ... read more |
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