| Packaging Options Expand In RF Power by RF DesignLine in EE Times RF & Microwave Designline |
August 9, 2010 -- RF power requirements for commercial wireless applications have evolved dramatically over the past few decades. Today, base station manufacturers demand power ICs capable of offering higher linearity to support higher order mod ... read more |
| Using In-Design Physical Verification to Reduce Tape-Out Schedules by Synopsys, Inc. in Design & Reuse |
August 2, 2010 -- Physical designers moving to lower foundry nodes worry about how to verify and deliver a design that is free of DRC violations while meeting their tape-out schedule. This can be quite challenging given that the number and compl ... read more |
| Use XML to Build ASIC or SOC Design Specifications by SiBEAM, Inc. in EE Times Embedded |
July 31, 2010 -- In a semiconductor company, the ASIC engineers design the hardware, and the hardware specification is distributed to other teams for hardware validation, embedded software development, and data-sheet documentation. Unfortunately ... read more |
| Protect Your goal with Post-Silicon Formal Verification by Jasper Design Automation in Design & Reuse |
July 19, 2010 -- SOC designers are learning the benefits of applying high-capacity formal verification techniques at every stage of the design. Our formal tools are powerful and versatile enough for a wide variety of tasks such as architectural ... read more |
| ESL Synthesis: Tips for Implementing a Viable ESL-Synthesis Flow by Gary Smith EDA in EDN Magazine |
July 15, 2010 -- As with any other technology, ESL invites squabbling among vendor technologists and early adopters about the goal of synthesis. One goal seems to capture the key aspects from a user perspective: An ESL-synthesis platform enables ... read more |
| Design Quality and Its Impact On Design Closure by Atrenta, Inc. in EDN Magazine |
July 15, 2010 -- The cost of SOC (system-on-chip) design continues to skyrocket, market windows continue to shrink, and design complexity continues to grow exponentially. These challenges are only a few of those that SOC designers face. In an ef ... read more |
| EM Simulation for EMC: Keeping a Lid on Interference by EDN Magazine |
July 15, 2010 -- EM simulation for EMC: keeping a lid on interference imageSimulating your product’s EM (electromagnetic) radiation will help ensure that you pass FCC (Federal Communications Commission) and CE (Conformité Européenne) tests and w ... read more |
| Accelerating the Time to IC Layout by EDA Solutions, Ltd. in EE Times EDA Designline |
July 14, 2010 -- With the move to nanometer geometries, IC design is becoming considerably more complex and time consuming. At the same time, analog content is increasing, reflecting strong growth in wireless and sensing technologies, and drive ... read more |
| Customized FPGA board for ASIC Prototyping: A Novel Approach with Pre-designed Blocks and Modular FPGA by in Design & Reuse |
July 15, 2010 -- Readily available off-the-shelf FPGA boards for ASIC prototyping brought significant advantages for SOC designers, yet there are many inherent challenges. A designer may have many reasonably priced off-the-shelf product options ... read more |
| IP Re-Engineering and Design Methodology by MindTree, Ltd. in Design & Reuse |
July 6, 2010 -- Today SOCs are becoming increasingly complex with hundreds of IPs being reused, integrated and further translated into millions of transistors in the design process. Each IP used in these SOCs evolves from one stage to another st ... read more |
|
