| Building Cost-Effective and Robust SOC-based Network Appliances by MosChip Semiconductor Technology, Ltd. in EE Times Embedded |
May 17, 2010 -- Today, consumers and businesses expect secured access to their information or content on demand anywhere at any time. As digital media is now a standard for audio/video (AV) content, its access and delivery has become very comple ... read more |
| A Novel Mesh Architecture for On-Chip Networks by Design & Reuse |
May 6, 2010 -- 2D Mesh is a very popular topology in network-on-chip due to its facilitated implementation, simplicity of the XY routing strategy, and the network scalability. On the other hand, 2D Mesh has some disadvantages such as long networ ... read more |
| The Need for Variable Precision DSP Architecture by Altera Corp. in EE Times Programmable Logic Designline |
May 5, 2010 -- Two fundamental trends driving the electronic infrastructure business are the need for higher data (and increasingly mobile) bandwidth and the need for higher resolution video. While somewhat distinct, these trends are overlapping ... read more |
| The Documentation Challenge by Oasys Design Systems in EE Times EDA Designline |
May 3, 2010 -- As a customer, how many times have you purchased a product and become frustrated because of the lack of good product documentation? You could be reading something simple like an Installation Guide for a household product or a comp ... read more |
| Powering Down: Enabling a Power Regression Flow for SoC Design by Calypto Design Systems, Inc. in EE Times Embedded |
May 3, 2010 -- Growing energy costs and the "green" revolution are driving designers to reduce the power consumption of SoCs used in today’s electronics systems. The most common method for optimizing power in these complex circuits is through cl ... read more |
| Using Unified Modeling Methods to Reduce Embedded Hardware/ Software Development by Cadence Design Systems, Inc. in EE Times Embedded |
May 10, 2010 -- Today's Internet devices are powered by sophisticated electronic circuits driven by multiple layers of software. These circuits are so complex they are called system-on-chip (SOC) because they contain all the sub-components of a ... read more |
| Doing C-code Generation Better: From Graphical Code to Embedded Target by National Instruments Corp. in EE Times Embedded |
May 3, 2010 -- One challenge designers face is the need to translate their algorithms into code for use in embedded targets. The task has proven to be long and prone to error. This article examines how the use of high-level design tools and C co ... read more |
| DDGEN: An Automated Device Driver Generation Tool for Embedded Systems by Design & Reuse |
May 3, 2010 -- This article describes a methodology for automatically generating device drivers for embedded systems. The authors formally specify the device behavior and attributes in an input specification called DPS (device programming sequen ... read more |
| Implementing Different Power Features In an IP by Synopsys, Inc. in Design & Reuse |
April 29, 2010 -- This article focuses on methods of defining power features based on the functionality of the design. It explains how power states can be defined and how different power features can be implemented for different power states in ... read more |
| Integrating Analog Video Interface IP Into SoCs Delivers Superb Image Quality: Part 2 by Synopsys, Inc. in EE Times EDA Designline |
April 29, 2010 -- Analog video interfaces are essential components of digital home and personal entertainment systems. This is mainly due to their ability to deliver very high image quality with very low power consumption while maintaining compa ... read more |
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