| Polyphase Techniques Let You Create Large Filters In Smaller Implementations In Mid-Range FPGAs by Lattice Semiconductor Corp. in EDN Magazine |
March 18, 2010 -- Digital signal processing is ubiquitous in modern electronic systems, from MP3 players to digital cameras to wireless handsets. One of the mainstays of a DSP designer’s tool box is the FIR (finite-impulse-response) filter. The ... read more |
| Picking the Right System Design Methodology for Your Embedded Apps - Part 3: Quality Assurance by EE Times Embedded |
March 17, 2010 -- The quality of a product or service is judged by how well it satisfies its intended function. A product can be of low quality for several reasons, such as it was shoddily manufactured, its components were improperly designed, i ... read more |
| Building Quality Assurance Into Your Hardware: EDA Is Not Enough! by Satin IP Technologies in EE Times EDA Designline |
March 17, 2010 -- Good EDA tools, even combined within well-automated flows, are not enough to produce quality designs, whatever those designs are for software, systems-on-chip (SOCs), integrated circuits (ICs), intellectual property (IP) or emb ... read more |
| Picking the Right System Design Methodology for Your Embedded Apps - Part 2: Informal Requirements and Formal Specifications by EE Times Embedded |
March 16, 2010 -- Before designing a system, we need to know what we are designing. In this context, the terms "requirements" and "specifications" are used in a variety of ways - some people use them as synonyms, while others use them as distinc ... read more |
| The Evolution of FPGA Coprocessing by Altera Corp. in Electronic Products Magazine |
March 1, 2010 -- The architecture of an FPGA allows the implementation of many algorithms where the sustained performance is much closer to the device’s peak performance than when using either a quad-core CPU or a general-purpose graphics proces ... read more |
| Power Delivery Network Design Requires Chip-package-system Co-Design Approach by Apache Design Solutions, Inc. in EE Times EDA Designline |
March 15, 2010 -- The power delivery network (PDN) has traditionally been a disjointed design problem with chip, package and board engineers doing their part of the design with margins assumed for the other parts. As 45-nm designs become more co ... read more |
| Verification of a USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment by Evatronix SA in Design & Reuse |
March 15, 2010 -- This article describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for synthesis and SystemC TLM mo ... read more |
| A Flexible, Field-Programmable ROM Replacement by Sidense Corp. in Design & Reuse |
March 15, 2010 -- For large amounts of on-chip code and data, mask read-only memory (ROM) provides an inexpensive and easily programmed storage mechanism. However, the inability to configure ROM after wafer processing means that information stor ... read more |
| Picking the Right System Design Methodology for Your Embedded Apps - Part 1: Why Design Methodologies? by EE Times Embedded |
March 15, 2010 -- Most real modern embedded system designs are inherently complex, given that their functional specifications are rich and they must obey multiple other requirements on cost, performance, and so on. As a result, we need methodolo ... read more |
| Selecting an Embedded MCU: How to Avoid the Evaluation Trap? by Dolphin Integration in Design & Reuse |
March 11, 2010 -- The main goal of this article is to focus on the difficulties encountered by SOC integrators when selecting an embedded microcontroller (MCU). Indeed, the selection is based on MCU performances, but the comparison can be diffic ... read more |
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