| Combating Congestion In High-performance, Low-cost SOCs by Freescale Semiconductor, Inc. in EDN Magazine |
February 23, 2010 -- Most semiconductor giants are cutting down on manufacturing costs by conserving on the die area. Fewer metal layers for interconnects saves additional mask-generation expenses. It also saves the manufacturing time in a semic ... read more |
| High-Level Synthesis, Verification and Language by Forte Design Systems, Inc. in EE Times EDA Designline |
February 22, 2010 -- The preferred high-level design methodology proceeds from high-level code to RTL code. Good verification practice requires that the input to high-level synthesis (HLS) be verified first, via simulation (or some other analyti ... read more |
| Tuning C/C++ Compilers for Optimal Parallel Performance In Multicore Applications: The Compiler Optimization Process - Part 2 by Intel Corp. in EE Times Embedded |
February 21, 2010 -- As a follow-on to Part 1, which included, among other things, an overview of compiler optimization as it relates to parallelization of code for multicore applications, in this second part in this series, the discussion will ... read more |
| Analog and Mixed-Signal Modeling Approaches by MindTree, Ltd. in Design & Reuse |
February 18, 2010 -- This article provides an insight into various approaches followed for analog and mixed-signal (AMS) modeling and the associated challenges. The emphasis is on analyzing various approaches and finally providing options that c ... read more |
| Traffic Management for Optimizing Media-Intensive SOCs by ARM in Design & Reuse |
February 18, 2010 -- The drive to constrain product costs and power consumption places severe limits on system designers, particularly with external memory bandwidth. To increase performance, designers need to focus on efficient use of this syst ... read more |
| Tuning C/C++ Compilers for Optimal Parallel Performance In Multicore Applications - Part 1 by Intel Corp. in EE Times Embedded |
February 18, 2010 -- An important first step for an embedded systems developer who wants to take advantage of parallelism via multithreading or partitioning in his or her multicore design is to increase the scalar performance of the application. ... read more |
| Leveraging FPGA and CPLD Digital Logic to Implement Analog-to-Digital Converters by Lattice Semiconductor Corp. in EE Times Embedded |
February 18, 2010 -- Designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function components on their printed ci ... read more |
| How Low Can 32-bit Processors Go? by EDN Magazine |
February 18, 2010 -- As 32-bit processors approach price parity with 8-bit processors, will that parity change the market for 8-bit processors? Moore’s Law observes that the number of transistors doubles for the same area every two years. The r ... read more |
| Reusable VHDL IP In the Real World by RF Engines, Ltd. in Design & Reuse |
February 18, 2010 -- Reuse has been an industry buzzword for years now. It is hardly a new idea, and probably goes back as far as the time when man first realised he could use the same fire both for keeping warm and for roasting his sabre-tooth ... read more |
| Adapting MCU Software to Meet Your Design Needs by Texas Instruments, Inc. (TI) in EE Times Embedded |
February 16, 2010 -- As the world continues to go digital, microcontrollers (MCUs) are being introduced to more applications than ever. New televisions use MCUs to increase the contrast ratio with LEDs. Lawnmowers can be automated with the help ... read more |
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