| Chip Synthesis: A New Approach to RTL Implementation by Oasys Design Systems in EE Times EDA Designline |
February 16, 2010 -- Traditional synthesis is coming apart at the seams, especially for designs larger than 20 million gates. Since it relies on gate-level optimization, traditional synthesis is very limited in the size of block that it can hand ... read more |
| Integrating Static Analysis with a Compiler and Database by Embedded Computing Design |
February 16, 2010 -- Advanced static-analysis tools are becoming increasingly critical in embedded systems development. Going well beyond older static analysis tools that were, in effect, coding style checkers, new tools statically analyze a sou ... read more |
| How Model-Driven Testing Can Generate Code-Based Testing Results by Embedded Computing Design |
February 16, 2010 -- In the systems and software testing community, generating code-based results is considered the gold standard for software testing. But increasing software complexity and shrinking time-to-market windows have forced many orga ... read more |
| What’s Next for Microcontrollers? by Texas Instruments, Inc. (TI) in Embedded Computing Design |
February 16, 2010 -- Throughout 2009, the level of innovation in companies from the top of the electronics supply chain to the bottom increased significantly as business groups eschewed competition in crowded markets with marginal improvements i ... read more |
| Green In: Multi-Engine GPS, DIMM Buffers, and Health-Certified USB Stack by Embedded Computing Design |
February 16, 2010 -- Connectivity is becoming more and more important, with establishing and maintaining a connection at low power being the objective. In this installment of Deep Green, we review a GPS receiver, a new class of DIMM modules, and ... read more |
| Green Up: Leading Edge of "Green" Mixed-Signal by Embedded Computing Design |
February 16, 2010 -- A couple years ago we started hearing about how Moore’s Law was running into the laws of physics. To keep getting faster, digital circuits had to undergo some fundamental research and rethinking. With that, we’re seeing both ... read more |
| Guidelines for Complex SOC Verification by eInfochips, Ltd. in EE Times EDA Designline |
February 15, 2010 -- Almost 60 to 70% of time in the ASIC cycle is occupied by functional verification and so, the main aim of this article is to provide overall guidelines in verification. More specifically, on the adoption of various planning ... read more |
| Re-Configurable Platform for Design, Verification and Implementation of SOCs by MindTree, Ltd. in Design & Reuse |
February 11, 2010 -- We propose a new methodology flow which will allow the visual definition of a complex SOC through instantiation of parametric IP such as processors, SDRAM controllers, DMA engines, on-chip buses, peripherals, switch matrices ... read more |
| Partitioning an ASIC Design Into Multiple FPGAs by Synopsys, Inc. in EE Times Programmable Logic Designline |
February 10, 2010 -- Most of today's system-on-chip (SOC) designs rely on field-programmable gate arrays (FPGAs) as a way to accelerate verification, start software development early and validate the whole system before committing to silicon. Th ... read more |
| Debugging and Analysis with SystemVerilog Testbench by SpringSoft, Inc. in EDN Magazine |
February 4, 2010 -- The verification component of SystemVerilog has dominated the rapid adoption of the language. The new verification syntax in the language allows for dramatic productivity gains in the verification cycle, which itself is now t ... read more |
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