| Reducing Embedded Software Bugs Using Static Analysis and Coding Rules by EE Times Embedded |
January 19, 2010 -- Software bugs are notoriously difficult to eradicate. Traditional quality assurance techniques like testing and software inspections (sometimes called code reviews) find serious bugs, but too many bugs slip through. This is o ... read more |
| Low-Power Design Is Here to Stay by Synopsys, Inc. in EE Times EDA Designline |
January 6, 2010 -- Low-power design is not new. Extending battery life for mobile devices meant playing design tricks to conserve energy in every possible way. The desire to integrate a system on a chip and reduce overall cost led designers to r ... read more |
| Architecture-Oriented C Optimizations by CEVA, Inc. in Design & Reuse |
January 14, 2010 -- Know your hardware! That's what it's all about. Using programming guidelines derived from the processor's architecture can dramatically improve performance of C applications. In some cases, it can even make the difference bet ... read more |
| Using An FPGA to Tame the Power Beast In Consumer Handheld MPUs by eInfochips, Ltd. in EE Times Programmable Logic Designline |
January 13, 2010 -- The consumer handheld market is growing by leaps and bounds. With more processing power and increased support for more applications, portable products are cross-pollinating with traditional computing systems even as the produ ... read more |
| Low-power LDPC Decoder Created Using High-Level Synthesis by Synfora, Inc. in EE Times EDA Designline |
January 13, 2010 -- With the popularity of mobile wireless devices soaring, the wireless communication market continues to see rapid growth. However, with this growth comes a significant challenge. Many applications, such as digital video, need ... read more |
| Deterministic Dynamic Memory Allocation and Fragmentation in C and C++ by Mentor Graphics Corp. in EE Times Embedded |
January 11, 2010 -- In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. However, the handling of such dynam ... read more |
| A Real Solution for Mixed Signal SOC Verification by Intrinsix Corp. in EE Times EDA Designline |
January 7, 2010 -- As more complex, mixed signal system-on-chip (SoC) designs continue to stress verification methodologies and schedules, designers need new approaches in solving today's test challenges. Mixed-signal verification presents a uni ... read more |
| Under the Lid: Analog Test Is Suddenly the Critical Ingredient by EDN Magazine |
January 7, 2010 -- ATPG (automatic-test-pattern generation), BIST (built-in self-test), and structural-test techniques have kept digital-test costs nearly constant during the explosion in digital complexity. Without these tools, however, as anal ... read more |
| Power Supply Design Considerations for Modern FPGAs by National Semiconductor Corp. in EE Times Programmable Logic Designline |
January 6, 2010 -- Today's FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, power supply requirements may be more demanding, requiring special attention to features deemed less important in past ... read more |
| Determine IC Transient Thermal Behavior to Prevent Overheating by Maxim Integrated Products, Inc. in EDN Magazine |
January 6, 2010 -- This article presents a method for predicting thermal behavior in integrated circuits. After characterizing thermal behavior, we formulate a mathematical model that simulates transient temperatures within the chip. We introduc ... read more |
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