| Duolog Tools Auto-Generate OVM Verification Environment | | |
February 23, 2010 -- Duolog Technologies today announced that its Socrates chip-integration platform can now auto-generate a complete OVM verification environment, using version 1.0 of the OVM register package recently released by Mentor Graphics. Auto-generating a complete OVM verification environment liberates verification teams from the tedious and error-prone task of building and debugging verification environments, allowing them to concentrate on verifying their designs.
"As a member of the Mentor Graphics Questa Vanguard Partnership (QVP) program, Duolog demonstrates the benefits of collaboration to advance verification productivity," said Dennis Brophy, Director of Strategic Business Development, Mentor Graphics. "Duolog’s OVM auto-generation solution accelerates significant user adoption of the OVM 1.0 Register Package."
The platform is an Eclipse-based suite of tools for assembling complex SOC, ASIC and FPGA designs. Socrates employs extensive DRC checks to verify design integrity and includes a fully-customizable suite of output generators to auto-create design, verification and software collateral. Auto-generation of design views from a central, verified source ensures that engineering teams remain synchronized at all times, and that costly bugs due to misalignment, miscommunication or misinterpretation are eradicated.
Go to the Duolog Technologies website to find additional information.
| E-mail Duolog Technologies for more information.
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| Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, Open Verification Methodology, OVM, system-on-chip, SoC, Socrates, Duolog Technologies, Socrates
| | 597/30804 2/25/2010 1420 152 | |
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| | 0.421875 |
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