March 8, 2010 -- eASIC Corp. announced the immediate availability of Aeroflex Gaisler's next generation LEON processor, the LEON4, as part of its eZ-IP Alliance Core Library. LEON4 is a high-performance, 32-bit processor core based on the SPARC V8 architecture. The new LEON4 core complements the widely used LEON3 processor for high-performance embedded applications across a broad spectrum of demanding consumer and industrial applications.

The power- and size-optimized LEON4 is fully software compatible with previous LEON processors, yet with a performance increase of up to 50% at the same clock frequency. The LEON4 processor implements single-cycle load/ store instructions, as well as static branch prediction. The register file and internal load/ store data paths have been extended to 64-bits, while the data cache and bus interface can be either 64- or 128-bit wide. An optional Level-2 (L2) cache has also been added to the architecture, further improving performance on data-intensive and multi-core applications. The LEON4 processor delivers up to 1.7DMIPS/MHz or 0.35 SPECINT2000/MHz.

"We are pleased with the performance of this next generation processor on eASIC silicon," said Jiri Gaisler, CTO and Founder of Aeroflex Gaisler. "The low cost-point and low up-front development cost of eASIC devices coupled with our LEON4 embedded processing sub-systems now enable an excellent price/performance entry point for custom embedded chip designs."

"The LEON4 processor core provides our customers with a perfect alternative to traditional soft processor cores from FPGA vendors and prevents customers from being locked into proprietary FPGA vendor IP cores," said Jasbinder Bhoot, Vice President, Worldwide Marketing at eASIC Corporation. "With Gaisler, designers are provided complete solutions that include CPU cores, peripherals, software tool chain, development boards and technical support."

Availability