|Celebrate Accellera’s 10 Years of Standards Excellence at 47th DAC |
June 1, 2010 -- Accellera invites the electronic design community to attend its breakfast during the 47th Design Automation Conference (DAC) and learn more about its EDA and intellectual property (IP) standards. Accellera’s DAC breakfast, sponsored by Cadence, Mentor and Synopsys, will feature a standards update with an overview of how the Universal Verification Methodology (UVM) standard supports verification tool interoperability and gives IP and EDA users more choices, and a panel "UVM: Charting the New Territory." This event continues the celebration of Accellera’s 10 years of standards excellence.
As part of the DAC Tutorials, experts will present on Low Power from A to Z. This tutorial will cover Accellera Unified Power Format (UPF) standard, also known as IEEE 1801.
The Synopsys Standards Booth will showcase SystemVerilog (also known as IEEE Std.1800) verification-based interoperability and Accellera’s UVM Base Class library. At Synopsys Conversation Central, Accellera’s chair, Shrenik Mehta, will speak about Accellera’s role in industry standards. Accellera’s Verification Intellectual Property Technical Subcommittee (VIP-TSC) co-chairs, Thomas Alsop and Hillel Miller, will also talk about UVM at the Open Verification Methodology (OVM) World booth and at Synopsys’ Conversation Central.
About Accellera’s Breakfast Panel
The Accellera Breakfast and the Panel, entitled "UVM: Charting the New Territory," will be held between 7:30am and 9:00am, Tuesday, June 15, at the Anaheim Convention Center, Room 203B.
Accellera's VIP-TSC has been actively working on UVM and its Early Adopter release. Current features of UVM can be best described as the reflection of verification methodology in use by the industry. Listen to this panel of expert verification engineers and methodology developers debate what they would like to see in UVM by DAC 2011. Is it more of the same, some incremental stuff, radical new technologies, or keep-it-as-is status quo for you? This is the time to find out more, and even chime in with your own views. Moderated by Gabe Moretti, panelists include: Sharon Rosenberg, Cadence Design Systems; Hillel Miller, Freescale Semiconductor; Mohamed Elmalaki, Intel; Tom Fitzpatrick, Mentor Graphics; Janick Bergeron, Synopsys; and Stacey Secatch, Xilinx.
About the DAC Low Power from A to Z Tutorial
This tutorial is aimed at providing a comprehensive look at how low power design permeates all levels of the design process. It will cover UPF and case studies. Organized by Dennis Sylvester, University of Michigan, Ann Arbor, the speakers are: Robert Aitken, ARM, Ltd.; Vivek Chickermane, Cadence Design Systems; Steve Curtis, Intel; Godwin Maben, Synopsys; and Srinivasa R. Sridhara, Texas Instruments. The tutorial will run from 9:00am to 5:00pm, Monday, June 14, in the
Anaheim Convention Center, Room 210CD.
Other Accellera events
- Accellera Standards Discussions - Tuesday, June 15, Synopsys Conversation Central at Booth #595
- UVM, 1:30pm-2pm
- Accellera standards, 3:30pm-4pm
- Accellera UVM Talk - 11am-11:30am, Monday, June 14, OVM World, Booth #1350
- SystemVerilog and Accellera UVM - 9:00am-6:00pm, Monday, June 14 -Wednesday, June 16, Synopsys Standards Booth # 585
Go to the Accellera website for details.
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|Keywords: ASICs, ASIC design, custom IC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, Accellera, DAC2010, |
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