June 3, 2010 -- Vennsa Technologies, Inc. today launched OnPoint, its verification tool for automated debugging. Vennsa’s OnPoint automates the manual root cause analysis performed by verification engineers once a functional failure occurs. It picks up where simulation and formal verification tools leave off by automatically analyzing the problem and pointing to the exact lines of code where the failure can be fixed. This error localization process is performed with no intervention by the engineer.

"Verification is the bottleneck," remarks Dr. Andreas Veneris, President and CEO of Vennsa Technologies. "Deep in its core is a highly manual and time-consuming debugging task, a true nightmare for every engineer. In the past decade, several verification tasks have been automated, but debugging has all but been ignored. As design complexity increases, so does the pain of manual, GUI-based debugging. Our debug automation software changes that."

According to many technology roadmaps, debugging accounts for approximately 60% of the verification process, adding weeks or months of extra labor per design cycle. It is one of the most time-consuming tasks in the chip design cycle. As the consumer product’s life gets shorter and the cost of missing the market introduction gets higher, the delay associated with manual debug can undermine the whole business plan behind a product.

Locating and fixing bugs continues to be a mostly manual effort. These cyclical tasks are performed hundreds of times per design by multiple verification engineers and designers. Additional overhead is introduced as verification and design teams are sometimes geographically dispersed and not familiar with the intricate details of each other’s work. Engineers must trace manually through signals, navigate the source code and stare at waveform viewers to understanding the source of failure with little automation.

About OnPoint

OnPoint is a root cause analysis tool that locates the source of failures at the register transfer level (RTL) in assertions and stimulus with no user interference. It is based on scientific technology that spans over a decade. Once verification fails, OnPoint reads the design and the counter example from the verification tool to automatically return the root cause of errors. In early evaluations, design teams confirmed that it can slash the manual debugging effort by weeks or even months.

Further, can assist with debugging by fixing waveforms with insight on what correction is required and the exact cycles where the error is active during simulation. OnPoint can find all types of functional bugs in the RTL code, assertion or assumptions, including conceptual or high-level errors; state transition bugs; bugs in assertions, assumptions and constraints; incorrect assignments; wrong operations; wrong if/case conditions problems with module instantiation; or bad module wiring.

It includes support for the Verilog hardware description language, SystemVerilog, SystemVerilog Assertions, the property specification language (PSL) and the Open Verification Library (OVL). It runs on the Linux operating system.