June 9, 2010 -- Synopsys, Inc. today announced that it has collaborated with TSMC to validate Synopsys' custom design solution with TSMC's 28-nm interoperable process design kit (iPDK) and Analog/ Mixed-Signal (AMS) Reference Flow 1.0. TSMC's 28-nm reference phase-locked loop (PLL) design was used to validate Synopsys' comprehensive custom solution while demonstrating productivity-enhancing capabilities of the TSMC AMS Reference Flow 1.0.
The validated solution from Synopsys includes the Galaxy Custom Designer® implementation, HSpice® circuit simulation, CustomSim™ FastSpice simulation, StarRC™ parasitic extraction and IC Validator physical verification solutions. Through the TSMC AMS Reference Flow 1.0 validation, mutual customers can expect a comprehensive, productive and open custom design solution that helps them address the emerging challenges associated with advanced semiconductor processes.
New advanced process technology nodes, such as TSMC's 28-nm process, require that EDA tools address a deeper and broader set of design challenges. These new challenges include high-accuracy Spice models for layout-dependent effects, design-rule-driven layout with table-based design rule checking (DRC) rules, larger and more complex DRC rule sets and high-accuracy extraction. Each product in Synopsys' custom solution was validated against TSMC's AMS Reference Flow 1.0 to help ensure that customers can be more confident in meeting their design quality and timeline requirements.
"TSMC and Synopsys have been collaborating on enabling an open ecosystem for custom and analog/mixed-signal designs with iPDK," said S.T. Juang, Senior Director of Design Infrastructure Marketing at TSMC. "The TSMC AMS Reference Flow collaboration further expands our relationship to improve the broader analog/mixed-signal and custom design solution by validating advanced TSMC technology and Synopsys tools together."
Synopsys' custom flow for front-end design and simulation consists of the Custom Designer Schematic Editor (SE) with simulation and analysis environment, HSpice circuit simulator, CustomSim FastSpice simulator and Custom WaveView waveform analyzer. The front-end flow was validated to meet a variety of needs such as yield, multiple process corners and noise effect analysis. The Synopsys custom physical design and verification flow consists of the Custom Designer Layout Editor (LE) with schematic-driven layout (SDL) and SmartDRD technology, IC Validator physical verification and StarRC Custom parasitic extraction. This flow was validated to address the needs of productive rule-driven layout, full DRC/LVS signoff and high-accuracy 3D extraction with RC reduction. The entire Synopsys custom flow was validated with TSMC's 28-nm iPDK.
Go to the Synopsys, Inc. website to find additional information.