June 8, 2010 -- Avery Design Systems today announced its latest enhancements for the company's behavioral-level, simulation-central formal analysis tool, now offering improved reachability analysis, low-power verification, reset-controllability analysis, and DFT analysis at the RT-level.

Reachability analysis formally proves what RTL code and FSM state transitions are unreachable thereby helping to establish and justify coverage goals and simulation code coverage results. The latest enhancements now enable Insight to recognize more FSM modeling styles, perform deeper sequential enumeration using automatic guided search algorithms, and diagnose unreachable code and FSM transitions as either RTL bugs, testbench limitations, or redundant deadcode. Assertion synthesis has also been added covering a wide range of checks which can be exported and used in chip-level logic simulation.

Low-power verification finds X propagations caused by RTL problems in power-transition sequences which can be missed by logic simulation due to X-pessimism and X-optimism issues. Insight supports power-aware symbolic analysis and the UPF 2.0 standard. Now power transition sequences can be analyzed for possible retention, isolation, and reset problems. Chip-level analysis is supported using a fully automated flow including auto-partitioning of the chip and replay of VCD files comprising the power transition sequence simulations which are then formally analyzed.

Reset-controllability analysis addresses logic-simulation problems created by aggressive post-route physical-synthesis optimizations of the reset logic. Reset controllability formally proves that a design can be properly reset even when logic simulation is not deterministic due to X-pessimism.

DFT at-speed testability analysis can now be started earlier in the design process by performing accurate analysis on the RTL. After initial at-speed path transition testability coverage is generated and untestable paths categorized, Insight provides suggestions on how to harden the design for improved testability.