June 8, 2010 -- Oasys Design Systems today announced a multi-year strategic licensing agreement with Xilinx, Inc. for Oasys’ Chip Synthesis technology. The companies are not disclosing terms of the agreement or details regarding Xilinx’s long-term plans for implementing the technology for field programmable gate array (FPGA)-based design.
"With programmable chip sizes growing and complexity mounting, it was clear we needed to look at a new generation of synthesis to support the needs of our customers," says Vin Ratford, Xilinx’s Senior Vice President of Worldwide Marketing. "We were immediately impressed with Oasys’ Chip Synthesis technology for its speed, capacity, performance and quality of results."
According to Oasys, RealTime Designer, based on the company's Chip Synthesis technology, is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs. It synthesizes RTL code to placed gates in a single pass and in a fraction of the time traditional synthesis does. A unique RTL placement feature eliminates unending design closure and iterations between synthesis and layout.
Oasys will demonstrate RealTime Designer at the 47th Design Automation Conference (DAC) in Booth #202 June 14-16 at the Anaheim Convention Center in Anaheim, Calif.
Go to the Oasys Design Systems website to find additional information.