| Jasper Introduces Intelligent Proof Kits for Faster, More-Accurate Verification of SOC Interface Protocols | | |
December 14, 2010 -- Jasper Design Automation today introduced Intelligent Proof Kits for accelerated certification of advanced SOC interconnect protocols. Jasper Intelligent Proof Kits encapsulate critical behaviors for popular protocols such as ARM's AMBA, letting users quickly configure designs to the standard or adapt them to their own custom configurations. Intelligent Proof Kits are optimized for high-level verification with Jasper's ActiveDesign and JasperGold formal verification, and designers benefit from these kits especially in combination with Jasper's Visualize technology.
"The next evolutionary step for Proof Kits is to encompass more intelligence, more plug-and-play functionality, more automation and more flexibility," said Lawrence Loh, Jasper Vice President of Worldwide Applications Engineering. "We work very closely with our partners to ensure Jasper's Intelligent Proof Kits match the protocol specs precisely. In addition, Jasper Proof Kits are easily comprehensible by users, so they can be adapted for proprietary extensions to standard protocols."
Users can deploy Intelligent Proof Kits from early in the design cycle, all the way through verification. Automated features allow for rapid integration into the design. Users can visualize selected properties and analyze timing diagrams to understand property behaviors, and cross-reference to the specifications through ActiveDesign, and the design protocol properties can then be seamlessly proven in JasperGold formal verification.
Availability
Jasper Intelligent Proof Kits ship unencrypted with original source code to facilitate user customization and insights into the protocols themselves. Jasper is initially rolling out Intelligent Proof Kits for AMBA 3 and AMBA 4, followed closely by DFI, DDR and LPDDR versions.
Go to the Jasper Design Automation website to find additional information.
| E-mail Jasper Design Automation for more information.
Read more about Jasper Design Automation on SOCcentral.com |
| Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, on-chip interconnect, Jasper Design Automation,
| | 597/32772 12/15/2010 902 118 | |
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