Page loading . . .

  
 Category: News: News Archive 2010: Saturday, May 25, 2013
DS-5 Supports Boot Code, Kernel, Driver and Application Development for ARM Linux-Based Products  
 Printer friendly
 E-Mail Item URL

December 20, 2010 -- ARM announced today the release of the ARM Development Studio 5 (DS-5) v5.3, and the commercial availability of the DS-5 Linux Edition. DS-5 accelerates Linux and Android native code development by providing a powerful and intuitive development environment, including source editing, compilation, debug and performance analysis tools.

DS-5 is now available in two packages:
  • DS-5 Application Edition targets application development using a low-cost Ethernet or USB connection to the target.
  • DS-5 Linux Edition extends this functionality with support for platform bring-up, kernel and driver development. The debug connection to the target is provided by a DSTREAM debug and trace unit.

The DS-5 device configuration database contains implementation details for supported ARM processor-based ASSPs, including JTAG interface, resets, peripheral registers and trace architecture. The current list of supported platforms includes Atmel, Freescale, Marvell, NXP, ST, and TI catalog devices. All the user needs to do is select the target device from a pull-down list and connect to it. More devices will be added in future DS-5 releases.

DS-5 speeds up platform bring-up by providing access to coprocessor registers and enabling the use of hardware breakpoints and data access watchpoints. DS-5 also supports instruction trace to simplify the debug of timing-related software bugs and analyse performance-critical code.

When debugging kernel-space code, DS-5 provides information on kernel threads, processes and loadable modules. This is complemented by the display of memory-mapped peripheral registers as they appear in the ASSP's documentation, which removes the need to continuously check device datasheets when doing driver development.

For DS-5 Application Edition users, this release adds new functionality in the Streamline Performance Analyzer:
  • Android native application and library profiling
  • Support for Cortex-A9 processor targets running Linux SMP. Streamline shows core allocation for each thread over time, which simplifies code balancing and enables more efficient use of the target's resources

Availability

DS-5 v5.3 is available now for Windows and Linux host platforms, and can be evaluated for 30 days free of charge by downloading it from the DS-5 page on the ARM website.

Go to the ARM website to find additional information.

E-mail ARM for more information.

Read more about
ARM
on SOCcentral.com


Keywords: embedded systems, embedded system design, ARM-based microprocessors, MPUs, EDA, EDA tools, electronic design automation, development platforms, operating systems, operating system kernels, OS kernels, Windows, Linux, Android, ARM, Cortex,
597/32803 12/20/2010 573 114


Designer's Mall
0.375



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.597  0.453125