| IC Manage Announces Global Design Data Management for Synopsys’ Galaxy Custom Designer Solution |
June 10, 2010 -- IC Manage, Inc. today announced the integration of Synopsys’ Galaxy Custom Designer solution and IC Manage Global Design Platform (GDP). Engineers can now efficiently manage and share Custom Designer’s design data across ... read more |
| Magma Offers Free Trial of Titan Mixed-Signal Platform in Latest Phase of "Titan Up!" Program |
June 14, 2010 -- Magma Design Automation, Inc. today announced the opportunity to download a free-trial version of the Titan mixed-signal platform and analog design accelerators. This is the next phase of the "Titan Up!" program, which ai ... read more |
| Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories |
June 14, 2010 -- Synopsys, Inc. today introduced its Galaxy Characterization Solution. The Galaxy Characterization Solution is a comprehensive suite of tools architected to generate compact, highly-accurate libraries for the design and im ... read more |
| Synopsys Delivers Optimized Lynx Design System for Common Platform 32/28-nm Technology |
June 14, 2010 -- Synopsys, Inc. today announced it is delivering an optimized, pre-validated design environment for the Common Platform alliance (CPA) 32-/28-nm high-k metal gate (HKMG) technology based on Synopsys' Lynx Design System. Ac ... read more |
| Cadence Kick-Starts UVM Adoption with Open-Source Reference Flow Contribution to UVM World |
June 11, 2010 -- Cadence Design Systems, Inc. today announced a comprehensive open-source reference flow for system-on-chip (SOC) verification using the Universal Verification Methodology (UVM) standard. The flow lets engineers adopt adva ... read more |
| TSMC 28-nm AMS Referenced Flow Includes Silicon Frontline’s F3D Parasitic Extraction Software |
June 14, 2010 – Silicon Frontline Technology, Inc.'s F3D (Fast 3D) parasitic extraction software for post-layout verification, has been selected as part of TSMC’s 28-nm Analog and Mixed-Signal (AMS) Referenced Flow 1.0. F3D was chosen bec ... read more |
| TOOL Corp. Announces New Release of LAVIS Layout Visualization Platform |
June 14, 2010 -- TOOL Corp. has released LAVIS Version 10.0, its layout visualization platform software. In this version, the new "Route Trace function" has been incorporated that makes it possible to display timing information and easily ... read more |
| Pyxis Router Selected for TSMC 28-nm AMS Reference Flow |
June 14, 2010 -- Pyxis Technology, Inc. announced that its NexusRoute-HPC (high performance custom) router has been selected for use in the TSMC 28-nm Analog and Mixed-Signal (AMS) Reference Flow 1.0. NexusRoute-HPC was used within the T ... read more |
| Cadence Delivers Extensive Support for TSMC AMS Reference Flow 1.0 for 28-nm Process |
June 11, 2010 -- Cadence Design Systems, Inc. today announced its support for TSMC Analog/ Mixed-Signal (AMS) Reference Flow 1.0 for advanced 28-nm process technology. The reference flow enhancements deliver significant assistance ... read more |
| Cadence Delivers TLM-Driven Design and Verification, 3D-IC Design and Integrated DFM Capabilities to TSMC Reference Flow 11.0 |
June 11, 2010 -- Cadence Design Systems, Inc. today announced that transaction-level modeling (TLM)-driven design and verification, 3D-IC implementation and integrated DFM are among the many Cadence technologies and flows that have been i ... read more |
| New Release of Azuro Rubix Delivers 15% Increase In Clock Frequency and Full Support for CPF 1.1 |
June 14, 2010 -- Azuro, Inc. today announced version 1.4 of Rubix, the company’s clock concurrent optimization tool. This release deploys extensive refinements to the product’s underlying timing-driven placement, logic sizing, and useful ... read more |
| New Release of Azuro's PowerCentric Delivers 15% Reductions In Clock Insertion Delays and Full Support for CPF 1.1 |
June 14, 2010 -- Azuro, Inc. has announced version 5.2 of PowerCentric, the company’s clock tree synthesis tool. This release deploys a proprietary new criticality-aware clustering algorithm to further reduce clock-insertion delays by an ... read more |
| Agilent Technologies’ Device Modeling Software Enables Development of Hua Hong NEC’s RF Device Modeling Platform |
June 11, 2010 -- Agilent Technologies, Inc. today announced that China-based Shanghai Hua Hong NEC Electronics Company, Ltd. has successfully used Agilent’s IC Characterization and Analysis Program (IC-CAP) software to develop an RF devic ... read more |
| ARM Accelerates Software Development on Hardware Assisted Verification Systems with VSTREAM |
June 14, 2010 -- ARM has announced the availability of the ARM VSTREAM virtual debug interface; a fast and flexible virtual link that connects software debuggers to hardware-assisted verification systems. VSTREAM enables more efficient so ... read more |
| Micrologic Announces Newest nanoToolBox to Accelerate IC Physical Design Sign-Off |
June 14, 2010 -- Micrologic Design Automation, Inc. has announced its new interactive NanoToolBox platform, enabling designers to perform DRC, reliability and LVS checks interactively within Cadence’s Virtuoso and Springsoft’s Laker layou ... read more |
| Cadence Announces Comprehensive SOI Design Hub |
June 9, 2010 -- Cadence Design Systems, Inc. today introduced the Cadence SOI Design Hub, a new web portal that lowers the barriers to adopting silicon-on-insulator (SOI) technology through comprehensive silicon-proven design enablement s ... read more |
| Oasys Design Systems Announces Multi-Year Strategic Chip Synthesis Technology License with Xilinx |
June 8, 2010 -- Oasys Design Systems today announced a multi-year strategic licensing agreement with Xilinx, Inc. for Oasys’ Chip Synthesis technology. The companies are not disclosing terms of the agreement or details regarding Xi ... read more |
| Integrand’s EMX Validated for TSMC’s RF Reference Design Kit 2.0 |
June 11, 2010 -- Integrand Software, Inc. today announced that its electromagnetic (EM) simulator EMX has been validated for TSMC’s RF Reference Design Kit (RF RDK) 2.0 inclusion. The flow works within the Cadence Virtuoso environment and ... read more |
| GlobalFoundries Launches Global Partner Ecosystem |
June 10, 2010 -- At next week’s Design Automation Conference (DAC), GlobalFoundries will unveil a new platform to spur innovation in semiconductor manufacturing and help deliver exceptional service to chip designers. Called GlobalFoundrie ... read more |
| Paradigm Works Announces SystemVerilog FrameWorks Template Generator Support for UVM |
June 9, 2010 -- Paradigm Works, Inc. today announced that its SystemVerilog FrameWorks Template Generator software now supports UVM (Universal Verification Methodology). The UVM Template Generator takes user input parameters and automatic ... read more |
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