| Virage Logic Expands Suite of Certified, Fully Optimized Audio Codecs, Underscoring Investment In ARC Processors |
May 25, 2010 -- Virage Logic Corp. today announced an expanded suite of certified, fully-optimized audio codecs that provide users with a robust and complete solution for a broad range of system-on-chip (SOC) audio applications. The codec ... read more |
| Microchip Technology Introduces mTouch Projected Capacitive Touch-Screen Sensing Technology, Development Kit and 8-bit MCU |
May 25, 2010 -- Microchip Technology, Inc. today announced the availability of mTouch Projected Capacitive Touch-Screen Sensing Technology, the first in a series of patent-pending releases supporting projected capacitive touch-screen solu ... read more |
| ARM Physical IP Production Characterization System Utilizes Magma SiliconSmart Software |
May 25, 2010 -- Magma Design Automation, Inc. announced today that ARM has successfully utilized Magma’s characterization and modeling software suite to enhance and expand ARM’s production characterization system for Physical IP products ... read more |
| CAST Reference Design System Simplifies H.264 Video Compression Evaluation and Analysis |
May 25, 2010 -- The H264-REF H.264 Video Encoding Reference Design System from CAST, Inc. combines multiple hardware functions and essential software in a pre-integrated, well-documented package. The System is available now, running in ei ... read more |
| Richtek Licenses Virage Logic's AEON MTP Family of NVM IP for Advanced Analog and Power-Management Products |
May 25, 2010 -- Virage Logic Corp. today announced that Taiwan-based Richtek Technology Corp. has taken a license for Virage Logic’s AEON MTP (multi-time programmable) family of NVM (non-volatile memory) IP. Richtek selected Virage Logic’ ... read more |
| Duolog's Socrates Chip-Integration Hub Supports Cadence's EDA360 Vision |
May 25, 2010 -- Duolog Technologies today announced that its Socrates Chip-Integration Hub supports key elements of the EDA360 vision recently unveiled by Cadence Design Systems, Inc.. EDA360 cites the growing need for an Open Integration ... read more |
| ON Semiconductor Launches IPD2 Process Technology that Combines "HighQ" Performance and Small Size |
May 25, 2010 -- ON Semiconductor has introduced a new integrated passive device (IPD) process technology. An enhancement of the company’s existing HighQ copper (Cu) on silicon (Si) IPD technology, the new IPD2 process features a second 5- ... read more |
| Sigrity Introduces Pre-Layout System-Level Power Delivery Optimization |
May 25, 2010 -- Sigrity, Inc. today introduced the first solution for pre-layout selection and placement of decoupling capacitors for power-delivery networks in PCBs and IC packages. Implemented in a new version of Sigrity’s OptimizePI so ... read more |
| CST Announces Significant New Functionality for CST Microwave Studio Frequency Domain Solver in Version 2011 |
May 25, 2010 -- Computer Simulation Technology (CST) announces curved elements and domain decomposition will be available in the CST Microwave Studio frequency domain solver in the next major release.
Engineers designing narrowband ... read more |
| SpringSoft's Laker Layout Supports TSMC 40-nm Technology with Interoperable PDK |
May 25, 2010 -- SpringSoft, Inc. has announced support for the 40-nm interoperable process design kit (iPDK) introduced by TSMC. This builds on SpringSoft’s support of the industry’s first iPDK developed by TSMC for its 65-nm RF pr ... read more |
| STMicroelectronics Announces 32-nm Design Platform for Next-Generation SOCs for Networking Applications |
May 25, 2010 -- STMicroelectronics today announced full availability of a 32-nm technology platform for the design and development of leading-edge ASICs for networking applications. Central to the new 32-nm SOC design platform, which impl ... read more |
| TowerJazz to Provide ARM Low-Power Libraries for 130-nm SiGe BiCMOS and RF CMOS Platforms |
May 25, 2010 -- TowerJazz today announced that it will be providing ARM physical IP low-power standard cells and memory libraries for TowerJazz’s new 130-nm SiGe process (SBL13) and its 130-nm RF CMOS process (TSL13). TowerJazz is ... read more |
| UMC Uses Silicon Frontline's Field Solver to Generate Reference Extraction Data |
May 25, 2010 -- Silicon Frontline Technology, Inc. (SFT) announced today that its F3D (Fast 3D) extraction software for post-layout verification has been qualified by United Microelectronics Corp. (UMC) as the reference field solver for ... read more |
| Tensilica and Iberium Partner for Solutions for DTV Market |
May 25, 2010 -- Tensilica, Inc. and Iberium Communications, Inc. have established a partnership to develop solutions for digital television (DTV). Tensilica is the leading provider of dataplane processors (DPUs) for system-on-chip ... read more |
| Menta Unveils eFPGA Creator Development Suite to Create Customizable Programmable Logic Architecture |
May 25, 2010 -- Menta S.A.S. today announced eFPGA Creator, a complete development tool suite that lets designers create customizable programmable logic architecture. By providing full control over the parameters of the embedded-FPGA stru ... read more |
| Altium Adds Aldec FPGA Simulation Technology to Altium Designer |
May 25, 2010 -- Altium, Ltd. and Aldec, Inc. have signed an OEM agreement that adds Aldec's FPGA simulation capabilities to Altium Designer. This agreement adds an extra dimension for electronics designers working with FPGAs and pr ... read more |
| Innopower Announces Availability of Faraday USB 3.0 Physical Layer IP |
May 24, 2010 -- Innopower Technology Corp. today announced the availability of the USB 3.0 PHY IP from Faraday Technology, which has successfully passed USB-IF (USB Implementers Forum) SuperSpeed certification and obtained the compliance ... read more |
| Tabula’s CTO Steve Teig to Speak During DAC Luncheon |
May 25, 2010 -- Steve Teig, president and chief technology officer (CTO) of Tabula, Inc., will describe an approach to move beyond von Neumann computing during a luncheon hosted by the IEEE Council on Electronic Design Automation (CEDA) a ... read more |
| Analog FastSpice Multi-Core Parallel (MCP) Delivers Up to 50x Speedup |
May 25, 2010 -- Berkeley Design Automation, Inc. today announced the Analog FastSpice (AFS) Multi-Core Parallel (AFS MCP) operating mode for its unified circuit verification platform (AFS Platform). AFS MCP automatically runs corners, swe ... read more |
| Compaan Design Releases HotSpot Parallelizer for ISO C |
May 24, 2010 -- Compaan Design has released the Compaan HotSpot Parallelizer for ISO C, supporting x86-multicore runtime verification and Xilinx FPGA code generation. This product integrates Compaan Design’s parallelization, streaming an ... read more |
|
