|Publication: EE Times EDA Designline|
Contributor: Mentor Graphics Corp.
February 21, 2011 -- Manufacturing closure has become a key design challenge at smaller technology nodes such as 32nm and 22nm. Starting at 45/40nm, the increasing complexity of design rule checks and design-for-manufacturing rules began to stress traditional physical-design flows. This trend is expected to continue and worsen at the 32/22-nm nodes, where manufacturing closure may become a serious bottleneck in design schedules.
The source of the growing manufacturing sign-off challenge is the widening gap between manufacturing and design. Features get smaller, but the resolution available through lithography using 193-nm light sources is reaching its limits. As we move to 32nm and beyond, the lithographic process introduces increasing variability since diffraction patterns are sensitive to specific layout shapes, and focus on the wafer becomes more sensitive to vertical topology due to depth of field effects. These factors introduce significant variations in line with width, thickness, and other physical characteristics that affect the yield and performance of ICs.
By Ivailo Nedelchev and Sudhakar Jilla. (Nedelchev is Principal Technologist, Place and Route Division, Mentor Graphics Corp. and Jilla is Marketing Director, Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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|Keywords: ASICs, ASIC design, custom IC design, EDA, EDA tools, electronic design automation, design for manufacturing, design-for-manufacturing, DFM, design for yield, design-for-yield, DFY, EE Times EDA Designline, Mentor Graphics, |
|599/33260 2/21/2011 1054 179|