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 Category: Magazine & Journal Articles Online: Article Archive 2011: Saturday, May 18, 2013
Facilitating At-Speed Test at RTL: Part 2  
Publication: EE Times EDA Designline
Contributor: Atrenta, Inc.
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April 20, 2011 -- Part 1 of this series discusses the problems with at-speed testing, and the various defect models and manufacturing test techniques. This part will tackle at-speed timing closure rules and at-speed coverage. It also looks into the at-speed coverage estimation and diagnosis of SpyGlass-DFT DSM.

The SpyGlass-DFT DSM product provides timing closure analysis and RTL testability for deep subµm (DSM) defects associated with at-speed testing. It is touted to provide accurate RTL fault coverage estimation for transition delay testing, together with diagnostics for low fault coverage, early in the design flow.

By Dr. Ralph Marlett and Kiran Vittal. (Marlett is Product Director for Atrenta, Inc. and Vittal is Product Marketing Director, Atrenta, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
Atrenta, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, design for test, design-for-test, DFT, EE Times EDA Designline, Atrenta,
599/33792 4/20/2011 728 124


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