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 Category: Magazine & Journal Articles Online: Article Archive 2011: Friday, May 24, 2013
Reduce SOC Device/ Package Leakage/ Power with Improved Power-Management Protocols  
Publication: EE Times Embedded
Contributor: Freescale Semiconductor, Inc.
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June 27, 2011 -- To reduce the design and packaging cost, SOCs are usually developed satisfying a superset of demands of multiple customers. To target the customers who do not need the complete functionality, the usual solution is to offer them only a subset of that functionality through the judicious use of packaging and pin-out options. This, however, leads to inclusion of logic which might be needed by one customer and not by others.

A byproduct of this strategy is that the extra unused logic is not used in the lower functionality variants of the SOC and still contributes to the overall leakage. This is because it still also shares the same power network as the rest of the logic. Described here is a way to use power domain partitioning to reduce the leakage in lower variants by taking advantage of package-configuration information.

By Kushagra Khorwal, Abhishek Kumar, Mayank Verma, and Shailesh Kumar. (All the authors are with Freescale Semiconductor, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Embedded website.

Read more about
Freescale Semiconductor, Inc.
on SOCcentral.com

Keywords: embedded system design, embedded systems, computer system design, general-purpose computers, power analysis, power optimization, power management, Freescale Semiconductor, EE Times Embedded,
599/34304 6/27/2011 512 74


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