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 Category: Magazine & Journal Articles Online: Article Archive 2011: Saturday, May 18, 2013
Problems and Pitfalls with Signal Integrity at 10Gbps and Beyond  
Publication: EE Times Planet Analog
Contributor: Vitesse Semiconductor Corp.
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September 23, 2011 -- Experienced designers of 10-Gbps (10G) Ethernet, SONET/OTN, Infiniband (QDR/FDR), and Fibre channel (16/ 8GFC) products are well aware that the maintenance of signal quality is far more difficult at 10-Gbps speeds than in the 1- to 3-Gbps range. Those who are initiating their first designs in the 10-Gbps realm may have to confront new realities that will dominate signal-quality issues, as backplanes and network interfaces move into that speed range.

There are discontinuities which are encountered, not only at the level of the individual device, but also at the level of the board trace, and these influence both board layout and the choice of substrate materials (such as FR4). A properly shaped, "clean" transmit signal will look very different at the receiver.

Characterizing signal-integrity issues for line cards and backplanes at 10Gbps and above requires visualizing the design at board level and device level simultaneously.

By Kinana Hussain. (Hussain is the product marketing manager for the connectivity product portfolio at Vitesse Semiconductor Corp.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Planet Analog website.

Read more about
Vitesse Semiconductor Corp.
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Keywords: computer system design, general-purpose computers, special-purpose computers, embedded system design, embedded systems, EDA, EDA tools, electronic design automation, PCB design, signal integrity, noise, Vitesse Semiconductor, EE Times Planet Analog
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