| Many-Core: Finding the Best Multi-Processing Tile by Emulation and Verification Engineering (EVE) in EE Times EDA Designline |
August 29, 2011 -- Today you can purchase a microprocessor IP block, configure it, and commit it to silicon without having to worry about the underlying logic, not to mention the transistors implementing that logic. Depending on the processor yo ... read more |
| Cryptography in Software or Hardware: It Depends on the Need by Maxim Integrated Products, Inc. in EE Times Embedded |
August 28, 2011 -- Cryptographic algorithms are high-performance, secure engines that require considerable space in a design. When counter-measures are added to thwart security attacks, the space and memory requirements grow even more demanding. ... read more |
| Slack Scheduling Enhances Multicore Performance in Safety-Critical Applications by DDC-I, Inc. in EDN Magazine |
August 25, 2011 -- Designers optimize multicore processors for average-case execution time, often at the expense of worst-case, or longest, execution times. This trade-off presents significant challenges to developers of safety-critical software ... read more |
| The Realities of the Maximum-Supply-Current Specification for Op Amps by Analog Devices, Inc. (ADI) in EDN Magazine |
August 25, 2011 -- Most ICs' data sheets list a maximum supply current, but manufacturers often overlook the measurement conditions. For some rail-to-rail-output op amps, certain operating conditions can result in supply currents two to 10 times ... read more |
| Transaction Analysis and Debug Across Language Boundaries and Between Abstraction Levels by Mentor Graphics Corp. in Design & Reuse |
August 25, 2011 -- Transaction analysis and debug between multiple abstraction levels is now possible with current technology. This article will present an API and implementation for recording transactions from SystemC, C or C++, SystemVerilog, ... read more |
| Basics of Core-Based FPGA Design-Part 4: Implementing a Design by EE Times Embedded |
August 22, 2011 -- This last part in a four part series presents an example project concept that is based on an FPGA embedded hard core processor implementation. It addresses a complex design implementation that is beyond the scope of this serie ... read more |
| Basics of Core-Based FPGA Design-Part 2: System Design Considerations by EE Times Embedded |
August 21, 2011 -- There are a number of system design factors requiring consideration when implementing an FPGA processor. Some of those factors include the use of co-design, processor architectural implementation, system implementation options ... read more |
| Basics of Core-Based FPGA Design-Part 3: Picking the Right Core Options by EE Times Embedded |
August 21, 2011 -- The three common processor implementation models used in FPGA cores are the microprocessor, microcontroller, and specialty processor. A microprocessor is generally a stand-alone core with limited peripherals. Microprocessors a ... read more |
| Developing Processor-Compatible C-Code for FPGA Hardware Acceleration by Impulse Accelerated Technologies, Inc. in EE Times Embedded |
August 21, 2011 -- FPGAs are becoming increasingly popular with software teams to accelerate critical portions of their code. In most cases these teams already have processing stacks and applications written in C that target embedded microproces ... read more |
| e-MMC vs. NAND with Built-in ECC by Toshiba America Electronic Components, Inc. (TAEC) in EE Times Memory Designline |
August 18, 2011 -- As NAND flash continues to increase in density and decrease in cost per gigabyte, it has enabled more cost-effective storage. This benefits a wide (and constantly growing) range of digital consumer products. Selecting the most ... read more |
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