| In IP We Trust? by Altos Design Automation, Inc. in Chip Design Magazine |
April 1, 2011 -- What keeps SOC designers up at night? It's the fact that they are now integrating many third-party IP blocks into their next-generation 2011 chips yet they have little or no control on how these subcomponents were created, verif ... read more |
| EDA Tools for 3D IC Design by Cadence Design Systems, Inc. in Chip Design Magazine |
April 1, 2011 -- With development costs heading towards $ 100 million for the 32nm process node and below, monolithic mixed-signal systems-on-chip (SoCs) are becoming increasingly costly and time-consuming to develop. Design teams are looking fo ... read more |
| System-Level Design: Five Likely 2011 Trends by Cadence Design Systems, Inc. in Chip Design Magazine |
April 1, 2011 -- It's the start of a new year, and I think it will be a good year for system-level electronic design. Here are some things to look for in 2011. This is a discussion of broad industry trends, not a specific product or technology f ... read more |
| Get the Lowdown on Accellera's VIP and UVM by Accellera in Chip Design Magazine |
April 1, 2011 -- Many of you are probably wondering what's happening with Accellera's Universal Verification Methodology (UVM) effort, which debuted its Early Adopter (EA) release in May of last year. We're very close to a release that's current ... read more |
| The (Design) House Always Wins: How DFM Improves the Odds of Tape-Out Success by Mentor Graphics Corp. in Chip Design Magazine |
April 1, 2011 -- Girolamo Cardano, Abraham de Moivre, Pierre-Simon Laplace; these early explorers of statistics and probability weren't particularly interested in advancing mathematical frontiers. They were looking for ways to understand and imp ... read more |
| The Missing Pieces in Power Modeling; Who's Going to Provide Them by Chip Design Magazine |
April 1, 2011 -- The push to develop power models is growing at each node, and at 22nm it will be virtually impossible to proceed without one or more models for power. Providing these kind of models is easier said than done, however. Creating an ... read more |
| Analog Circuits Benefit from Scaling Trends by Synopsys, Inc. in Chip Design Magazine |
April 1, 2011 -- As CMOS technologies scale to smaller nodes, both benefits and challenges are created. There are advantages in speed and power due to lower capacitance loading and the lower supply voltage. Conversely, the reduction in intrinsic ... read more |
| Automating Design Rule Waivers in SOC IP Reuse by Mentor Graphics Corp. in Design & Reuse |
March 31, 2011 -- Intellectual property (IP) reuse, especially at the physical IP level, is a key component of the growing system-on-chip (SOC) ecosystem. However, with the increase in the amount and scope of custom and third-party IP integrated ... read more |
| Complete NAND Flash Solution: Logic, PHY and File System Software by Arasan Chip Systems, Inc. in Design & Reuse |
March 31, 2011 -- Designers using NAND Flash devices should follow the ONFI standard interface to ensure that their controller design will operate with devices from any vendor. The memories need both digital and analog interfaces between the dev ... read more |
| Attofarad Accuracy for High-Performance Memory Design by Mentor Graphics Corp. in EE Times EDA Designline |
March 30, 2011 -- The future is here; phone, web browser, email, photo and video, all in one device at your finger tips, simultaneously. The evolution of IC design is in part driven by the demand for more memory with higher performance. Advanced ... read more |
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