| Carefully Time the Adoption of Your Next-generation Processor by Embedded Insights, Inc. in EDN Magazine |
October 6, 2011 -- One of the first expressions I learned as a young embedded-system developer was "Smart money avoids Version 1.0." Back then, there was little expectation that even a compiler would be available to developers soon after the ava ... read more |
| 25-28Gbps SerDes Design and Implementation Challenges by MoSys, Inc. in Chip Estimate Corp. |
October 4, 2011 -- As data-rates increase, more and more companies are relying on the expertise of 3rd party IP vendors, such as MoSys, who make SerDes their lifeblood and can leverage the cost of developing an IP across multiple customers. MoSy ... read more |
| Debunking the Myth of the $100M ASIC by Adapteva, Inc. in Electronic Engineering Times (EE Times) |
October 3, 2011 -- A false belief that leading-edge chips cost up to $100 million to develop has severely decimated levels of venture capital investment in semiconductors, diminishing innovation in our industry and our economy. The fact is, engi ... read more |
| Reducing Turnaround Time with Hierarchical Timing Analysis by Synopsys, Inc. in EE Times EDA Designline |
October 3, 2011 -- The semiconductor industry accepts two facts: designs continue to grow in size and complexity, and time-to-market pressure is higher than ever.
I'll use the smart phone as an example to make my point. On a smar ... read more |
| Minimizing Yield Fallout by Avoiding Over and Under At-Speed Testing by Advanced Micro Devices, Inc. (AMD) in EE Times Embedded |
September 30, 2011 -- In the nanometer technology used for automotive SOCs, most defects on silicon are due to timing issues. Thus, at-speed coverage requirements in automotive designs are stringent. To meet these requirements, engineers expend ... read more |
| How to Design a Traditional Radio by Silicon Laboratories, Inc. in EE Times RF & Microwave Designline |
September 29, 2011 -- Radio technology has been around for more than a century, and traditional wheel-tuned radio products have been used for decades by countless listeners around the world. They provide a simple user interface based on a tuning ... read more |
| Concurrency Checkers Can Improve Multicore Process Performance by GrammaTech, Inc. in New Electronics Magazine |
September 27, 2011 -- To take advantage of performance improvements provided by multicore processors, it is essential to have a good command of concurrency. Yet most developers are accustomed to reasoning about programs from the perspective of a ... read more |
| Metrix-Driven Hardware/ Software System-Level Verification by NXP Semiconductors in Design & Reuse |
September 27, 2011 -- Industrial data shows that verification takes about 70% to 80% of the total project development time. With the increasing complexity of the SOC and with increasing software content in the sub-system, system level hardware/ ... read more |
| A Practical Approach to IP Quality Inspection by Atrenta, Inc. in EE Times EDA Designline |
September 26, 2011 -- If you are a chip designer working with third-party IP, you have learned that surprises, not always of the good kind, are an inevitable part of the package. And you are not alone; the use and cost associated with third-part ... read more |
| Dealing with the Pains of Technology Adoption by Cadence Design Systems, Inc. in Electronic Design Magazine |
September 26, 2011 -- Technologies for system-level design and their adoption have been a topic of debate in EDA well over a decade. Users and providers of system-level design technologies alike are watching the state of adoption, and like child ... read more |
|
