February 7, 2011 -- Mentor Graphics Corp. today announced that VIA Technologies, Inc., a fabless supplier of power-efficient x86 processor platforms, is adopting the Calibre PERC electrical rule-checking product to ensure that electrostatic discharge (ESD) protection meets established guidelines to help prevent circuit failures and design re-spins.

By helping ensure that designers have met all ESD protection rules, the Calibre PERC product contributes to the robustness of designs in portable and high-reliability applications. It also verifies the integrity of low-power designs that have multiple power domains by making a variety of leakage and resistance checks. The Calibre PERC product removes the burden of manual electrical rule-checking from designers, as it can be programmed to meet these general concerns as well as address unique customer requirements.

"Calibre PERC enables users to define electrical checks using both topology and geometric information. We use this tool to create a set of rules that preserve debugging experience from previous product ESD issues and prevent the same ESD failures from happening across many design sites," said Shelton Lu, Vice President of Manufacturing and Product Engineering in the CPU Platform R&D division of VIA. "This allows PERC to perform many critical checks for our design engineers. VIA has a very sophisticated methodology for how our ESD structures should be constructed, including rules for multiple power domains, back-to-back diodes and power/ ground clamp devices. Additionally, we also have checks that we perform on leakage paths and discharge path resistance. PERC provides our designers a solution to validate the robustness of our designs by giving us access to the necessary circuit, geometry and parasitic information to automatically perform checks that help drive the reliability of VIA's product offering."

"Calibre PERC introduces a new class of design rule checkers that provide the versatility and programmability needed for today's advanced designs, while working in the familiar Calibre platform that is integrated into all major EDA design flows and supported by all the major foundries," said Joseph Sawicki, Vice President and General Manager for the Design-to-Silicon division at Mentor Graphics.

More about Calibre PERC

The Calibre PERC product addresses a range of applications including validating that a circuit has sufficient protection against electrostatic discharge (ESD) events, and helping designers identify inappropriate connections between multiple power supplies in mixed-signal ICs. It helps ensure the completeness of circuitry needed to protect a device against ESD and ensures a higher level of ESD design rule compliance because it goes beyond traditional layout geometry-based checking to enable verification of specific device and interconnect structures and electrical characteristics. For example, it can identify the omission of required ESD protection on a schematic or netlist. It can also be used to look for errant signal paths and other soft connection errors such as well connection errors, floating devices, nets, or pins, incorrect voltage supply connections, excessive series pass gates, problem level shifter designs, antenna checks, floating wells, minimum "hot" NWELL width, and many others.

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