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 Category: News: News Archive 2011: Saturday, August 30, 2014
Accellera Chair Shishpal Rawat Talks about Roadmap for IP and System Design Standards at IP-SOC 2011  
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November 3, 2011 -- Accellera invites designers to hear Accellera chair Shishpal Rawat's invited talk on "The Roadmap for IP and System Design Standards" at IP-SOC 2011, December 7, Grenolbe, France.

System, software and semiconductor design activities are converging to meet the increasing challenges of creating SOCs. Accellera is working with OSCI and the SystemC working groups, as well as the IEEE and other standard bodies, to facilitate the creation of system design and IP standards that reduce the cost of electronic design and increase productivity. This presentation will cover our groups' standard activities — IP Tagging, IP-XACT, Open Verification Library (OVL), Standard Co-Emulation Modeling Interface (SCE-MI), Unified Coverage Interoperability Standard (UCIS) and Universal Verification Methodology (UVM) — the benefits of Accellera standards, their fit with SystemC, and the roadmap for adoption.

Go to the Accellera website to find additional information.

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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, EDA, EDA tools, electronic design automation, Accellera, IP-SOC 2011,
600/35260 11/3/2011 700 96
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