Page loading . . .

  
 Category: News: News Archive 2012: Friday, April 18, 2014
CAST Shipping New CAN Bus Controller IP Core  
 Printer friendly
 E-Mail Item URL

January 16, 2012 -- A new core from CAST, Inc. adds new capabilities to the company's long-time support for the Controller Area Network (CAN) Bus Protocol. The CAN-CTRL CAN Bus Controller IP Core conforms to the latest, 2.0B CAN Bus Protocol and ISO ISO 11898-1 Data Link Layer specifications.

Users have fully tested products using the core against the ISO 16845 Road Vehicles CAN Conformance Test Plan to verify its correct and complete functionality.

The ASIC or FPGA CAST CAN core implements a hardware controller for the CAN data link layer, handling data framing, transmission, reception and synchronization, and error reporting. The new core adds a configurable number of acceptance filters, a single-shot transmission mode for lower software overhead and faster buffer reloading, and several features similar to the PeliCAN mode of the popular Philips SIA1000 discrete chip. The latter include several important error-diagnosis and system-maintenance functions, including a programmable error-warning limit and a listen-only mode for better data traffic analysis.

"CAN has been a steady seller for us for many years, with a recent surge of growth for more demanding automotive control and communication systems," said Nikos Zervas, Vice President of Marketing for CAST. "This new CAN controller core offers the features an performance designers are now requesting, coupled with easy integration and CAST IP product support."

Availability

Sourced from partner Fraunhofer IPMS, the core is available now.

Go to the CAST, Inc. website to find additional information.

E-mail CAST, Inc. for more information.

Read more about
CAST, Inc.
on SOCcentral.com


Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, Controller Area Network (CAN), CAST,
601/37449 1/16/2012 569 102
Designer's Mall
Cinco De Mayo countdown banner
0.4057617



 Search for:
            Site       Current Category  
   Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Executive
Viewpoint

Progressive Static Verification Leads to Earlier and Faster Timing Sign-off


Graham Bell
VP of Marketing,
Real Intent

Executive
Viewpoint

Threading the Way
through
SOC Verification


Thomas L. Anderson
VP of Marketing,
Breker Verification Systems

Odd Parity

What? You Haven't Made Any Resolutions?


Mike Donlin
The Write Solution

Odd Parity Archive

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters



About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.601  0.4692383