February 20, 2012 -- PLDA has announced QuickPCIe, an advanced PCI Express interface IP solution featuring a high-performance configurable DMA. QuickPCIe is claimed to be a breakthrough in IP integration, standardizing on the AMBA AXI open interconnect protocol to provide a unified and scalable interface to user logic.
The integration of a scalable PCI Express interface IP and a high-performance AXI4 based DMA engine enables ease of development of complex FPGA designs with stringent performance requirements.
About QuickPCIe IP
Designed for Endpoint and Root Port applications, QuickPCIe is compliant to the PCI Express Specification revision 3.0 and to the AMBA AXI4 Specification v2.0.
QuickPCIe supports PCI Express x1, x2, x4, x8 and x16 interfaces at Gen1, Gen2 and Gen3 speeds (8.0GTps).
QuickPCIe built-in multi-channel DMA supports packet-based and block based data transfers through multiple AXI4 interfaces.
QuickPCIe supports Xilinx and Altera PCI Express Hard IP and PLDA PCI Express Soft IP.
"The combination of a hard or soft PCI Express IP with advanced DMA capability and a standardized user interface significantly accelerates time-to-market and encourages IP reuse," commented Stephane Hauradou, PLDA's CTO
Go to the PLDA website to find additional information.
