Page loading . . .

  
 Category: News: News Archive 2012: Saturday, May 25, 2013
Tensilica Lays Foundation for Software Programmable LTE-Advanced User Equipment PHY (Layer 1) in Less than 200mW  
 Printer friendly
 E-Mail Item URL

February 21, 2012 -- Tensilica, Inc. announced that it is driving the transition to LTE-Advanced and has already secured lead customers for its new product, the ConnX BBE32UE DSP (digital signal processor) IP core for baseband SOC (system-on-chip) designs.

Using the ConnX BBE32UE DSP core, coupled with Tensilica baseband dataplane processors (DPUs), a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) can be realized in less than 200mW (28-nm HPL process). It can also support 2G, 3G, LTE and HSPA+ standards.

The transition from LTE to LTE-Advanced can require up to a 5X algorithm and data-rate computation increase within a very tight power budget. Tensilica has worked with leading handset manufacturers to optimize the architecture and the instruction set of the ConnX BBE32UE for algorithms required by user equipment applications.

Tensilica's flexible, processor-based solution is ideal for LTE-Advanced because the new algorithms may well need changing during field and interoperability testing. Previous design methods with hard-wired implementations will not be able to provide the flexibility of algorithm updates, and most conventional wireless communications DSPs will fail to meet the power budget. With this new, very low-power DSP core and baseband DPUs, Tensilica can offer system developers a path to implement flexible, ultra-low-power PHY systems.

Data bandwidth, an important criterion for LTE-Advanced user equipment applications, is enhanced in the ConnX BBE32UE through the use of dual 256-bit load/ store units. In addition, designers can use Tensilica's proprietary Port (general-purpose I/O) and Queue interfaces to directly connect hardware blocks to the processing ALUs. This allows single-cycle dedicated access without the need to go over a system bus, hence reducing the required clock frequency and power consumption.

Like other members of Tensilica's ConnX family of DSPs, the ConnX BBE32UE is fully programmable in C. It is software compatible with other ConnX DSPs and supported by an optimized DSP library.

Availability

While early access customers now have access to ConnX BBE32UE, general product release is planned for the third quarter of 2012.

Go to the Tensilica, Inc. website to find additional information.

E-mail Tensilica, Inc. for more information.

Read more about
Tensilica, Inc.
on SOCcentral.com


Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, DSP cores, DSP, digital signal processing, digital signal processors, Tensilica, system-on-chip, SoC,
601/37857 2/22/2012 508 77


Designer's Mall
0.390625



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.601  0.46875