| SpringSoft and Synopsys Link Debug Technologies | | |
February 27 , 2012 -- SpringSoft, Inc. and Synopsys, Inc. today announced that they have linked SpringSoft's Verdi Automated Debug System with Synopsys' Protocol Analyzer. Part of the Synopsys Discovery VIP family, Protocol Analyzer helps engineers quickly understand, identify and debug protocols in their designs. Through this linkage, the identified protocol violations and errors are seamlessly passed to the Verdi environment for detailed signal-level analysis to rapidly pinpoint the root causes of violations.
As leading system-on-chip (SOC) designs incorporate multiple complex protocols, verification IP (VIP) has become a critical component of the verification environment, enabling engineers to reach their coverage goals within tight project schedules. With the increase in protocol complexity, protocol debug is now one of the most difficult and time-consuming aspects of SOC functional verification. This collaboration, implemented with SpringSoft's VIA (Verdi Interoperability Apps) platform, directly addresses these challenges by combining the protocol-centric debug capabilities in Protocol Analyzer with the advanced design-debug capabilities of the Verdi system.
"As protocol complexity has increased, efficient protocol debug has become an area of concern for the industry," said Janick Bergeron, Verification Fellow at Synopsys. "Addressing the protocol-debug challenge was one of our key areas of focus when developing our next-generation VIP. With this collaboration, our protocol debug technology is integrated with SpringSoft's design-debug technology to further enhance SOC verification productivity."
Verification engineers use VIP to test all SOC interface protocols, including ARM AMBA AXI4, USB 3.0, PCI Express, and others. Protocol Analyzer, available with the Synopsys Discovery VIP family, provides protocol-centric debug and unique capabilities that enable engineers to quickly understand protocol activity, identify bottlenecks and debug unexpected behavior by minimizing unnecessary detail and focusing on high-level protocol activity such as AXI transactions, USB transfers or PCI Express packets. The Verdi Automated Debug System, the cornerstone of SpringSoft's family of functional-closure products, accelerates the process of finding, analyzing and correcting the root causes of errors revealed during the verification of complex digital IP components, design modules or entire SOCs.
Go to the SpringSoft, Inc. website to find additional information.
| E-mail SpringSoft, Inc. for more information.
Read more about
SpringSoft, Inc.
and
Synopsys, Inc.
on SOCcentral.com |
| Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, verification IP, intellectual property, cores, SpringSoft, Verdi Automated Debug System, Synopsys, Protocol Analyzer,
| | 601/37923 2/28/2012 563 72 | |
|
|
|
| | 0.3896484 |
|
|
| | |
|
|
Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.
|
|
|
Exec Viewpoint
Maximizing the Value of Your Internal IP
Warren Savage
CEO, IPextreme
|
|
Exec Viewpoint
Yes, Virginia,
There Is a
Stitch-and-Ship
Dave Johnson
VP of Sales
Breker Verification
|
|
|
|
Barbara's Bytes
So, Just What
Is ESL
Barbara Tuck
Senior Editor,
SOCcentral
|
|
|
|
|
|
|
|
| Design Center |
| Whitepapers & App Notes |
|
|
|
|
|
| Live and Archived Webcasts |
|
|
|
|
|
| Newsletters |
|
|
|
|
|
|
About SOCcentral.com
Sponsorship/Advertising Information
|
|
|
