Page loading . . .

  
 Category: News: News Archive 2012: Wednesday, May 22, 2013
Lattice Announces Upgraded HDR-60 Video Camera Development Kit Featuring New GUI from Helion  
 Printer friendly
 E-Mail Item URL

February 29, 2012 -- Lattice Semiconductor Corp. hasy announced an upgrade to the Lattice HDR-60 Video Camera Development Kit, now enhanced with a Helion graphical user interface (GUI). The production-ready Lattice HDR-60 video camera development kit is based upon the LatticeECP3 FPGA family.

Pre-loaded with a plug-and-play evaluation image signal processing (ISP) pipeline based on IP cores from Lattice partner Helion GmbH, the kit reduces design time for embedded camera applications. The IP is capable of delivering 1080p performance at 60 frames/s with 2D noise reduction and high dynamic range (HDR). With a form factor designed to fit into commercially available camera housings and capable of supporting two sensors simultaneously, the kit enables rapid evaluation and prototyping of high-definition HDR video cameras for security and surveillance, traffic control, video conferencing and automotive applications. Schematics and layout files are available free to all purchasers, further accelerating time to market.

The Lattice HDR-60 will now sport a new GUI developed by Helion, making it even easier for developers to evaluate and configure the IP. Users will be able to change the target brightness, speed and algorithm of auto-exposure, choose between manual and automatic auto white balance with red-blue ratio control, change gamma and CCM values on the fly and adjust the position and transparency of overlays.

"Our first ISP release for the Lattice HDR-60 enabled developers to combine their desired IP in a very flexible manner with the LatticeMico32 microprocessor," said Dr. Arndt Bussmann, Chief Technology Officer of Helion. "The new GUI addresses the desire to configure and setup the IP for evaluation via an easy-to-use and flexible interface. Internal benchmarks in our labs, with our native coded modules on different FPGAs from different vendors, demonstrated the LatticeECP3 leads in speed, low gate count, low cost and low power consumption for image signal processing applications.”

The GUI can be used on Windows and Linux platforms, with support for different sensors including the Aptina AR0331 and MT9M024 and others.

Availability and Pricing

The enhanced GUI will be available for download March 19, 2012, at no additional charge to current and new customers of the Lattice HDR-60 video camera development kit.

Go to the Lattice Semiconductor Corp. website to find additional information.

E-mail Lattice Semiconductor Corp. for more information.

Read more about
Lattice Semiconductor Corp.
and
Helion GmbH
on SOCcentral.com


Keywords: FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, video, video processing, development kits, Lattice Semiconductor, Helion
601/37980 2/29/2012 531 71


Designer's Mall
0.4023438



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.601  0.4492188