March 14, 2012 -- SynaptiCAD, Inc. has released an updated version of its VeriLogger Extreme Verilog simulator. The new version supports compiling source files to symbolic libraries, enabling faster compiles of designs that share a common set of source files such as ASIC/ FPGA libraries.

This version also performs gate-level and cycle-based optimizations for faster simulation times (5X faster on gate level designs, 6X faster on designs that use cycle-based coding practices). Other enhancements include reduced memory consumption during compilation and simulation, faster design elaboration, increased compatibility with third-party simulator language-extensions, and support for more Verilog 2005 features.

SynaptiCAD is giving away free "no strings attached" six-month licenses for VeriLogger Extreme bundled with BugHunter Pro, its graphical debugging software. Free licenses will be available for both Linux and Windows versions of the simulator and debugger. Unlike the lower-cost simulators typically provided with FPGA tools, VeriLogger is being distributed without any code that slows down the simulator when run on larger designs, making it run over 10X faster than the competition on larger simulation runs.

Availability and Pricing