April 24, 2012 -- Solido Design Automation, Inc. formally announced today its High-Sigma Monte Carlo (HSMC) meta-simulator solution. Solido's HSMC, part of the Variation Designer product family, was released in October 2010 and is in use at 7 of the top 20 semiconductor vendors. It provides accurate, scalable and verifiable analysis and design solutions for memory chips, and is more than 100 times faster than Monte Carlo analysis.

Meta-simulation has historically been limited to simplistic methods, such as running corners or running Monte Carlo. Today, meta-simulation techniques can be much more powerful, addressing designer challenges and speeding up different analyses types in precisely-targeted ways. For example, rather than running 100 or 10,000 PVT corners just to search for the worst cases, a "Fast PVT" meta-simulator would analyze all the PVT corners and intelligently simulate only the small subset requires to identify the worst-case corners with confidence.

Meta-simulation goes beyond distributed processing; it also adds efficiency to high-value analysis capabilities such as: fast PVT analysis; fast extraction of statistical corners; and fast sensitivity analysis. An ideal meta-simulator for memory design measures yield-performance trade-offs out to 5 and 6 sigma, with the same accuracy as millions or billions of Monte Carlo simulations, but with 100X+ fewer simulations.

Solido's High-Sigma Monte Carlo key features for memory design