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 Category: News: News Archive 2012: Thursday, June 20, 2013
Carbon Design Systems and Cadence Partner for IP Optimization  
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May 24, 2012 -- Carbon Design Systems, Inc. and Cadence Design System, Inc. announced today availability of a Carbon Performance Analysis Kit (CPAK) to accelerate the intellectual property (IP) benchmark process. The CPAK incorporates a Cadence double-data-rate (DDR3) Memory Controller together with an ARM Cortex-A9 MPCore processor, and industry-standard benchmarks, such as those from EEMBC.

"Optimization of the processor to memory datapath plays a key role in the development of many leading-edge SOCs," remarked Rick Lucier, President and CEO at Carbon. "By partnering with Cadence to deploy this CPAK, we are enabling engineers to be more productive by benchmarking the same day they download the package from Carbon IP Exchange."

"The Carbon/Cadence Performance Analysis Kit executing CoreMark highlights the important role that industry standard benchmarks can play in the IP selection process," added Markus Levy, president of EEMBC.

"ARM power-efficient technology is at the heart of many products, ranging from embedded microcontroller applications to servers, network infrastructure and smart connected devices," commented Joe Convey, Director of Design Enablement, ARM. "Reference implementations, such as the Carbon/ Cadence Performance Analysis Kit, are important tools that allow ARM Partners to innovate more easily by quickly understanding capabilities of the Cortex-A9 processor."

About the platform

The Carbon/ Cadence offering is the latest addition to the library of Carbon Performance Analysis Kits available from Carbon’s IP Exchange web portal. This platform features an ARM Cortex-A9 processor and a Cadence DDR3 memory controller, along with configurable models for the interconnect fabric, DDR3 memory and memory PHY.

In addition, multiple configurable traffic generators are included as producers and consumers to model additional bus traffic. Included in the system is a software package that includes, among other tests, the CoreMark benchmark from EEMBC. The CPAK executes in Carbon's SoCDesigner Plus virtual prototype environment that delivers a rich suite of analysis and visualization tools.

Availability

The Carbon/Cadence CPAK is available now from Carbon's IP Exchange web portal. The ported CoreMark benchmarking software is available from www.coremark.org.



Go to the Carbon Design Systems, Inc. website for details.

E-mail Carbon Design Systems, Inc. for more information.

Read more about
Carbon Design Systems, Inc.
and
Cadence Design Systems, Inc.
on SOCcentral.com


Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, ARM-based microprocessors, MPUs, Carbon Design Systems, Cadence Design System,
601/38519 5/24/2012 501 58
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