May 29, 2012 -- Real Intent, Inc. today announced the release of version 4.1 of its Meridian Clock Domain Crossing (CDC) analyzer and the release of version 1.5.1 of its Ascent Lint tool. These new releases provide significant advances over the 2011 versions of the software.

"These new releases deliver deeper analysis without sacrificing speed or capacity," stated Prakash Narain, CEO of Real Intent. "Our low-noise reporting avoids burying designers with superfluous or incorrect results despite the ever-increasing complexity of designs."

The latest Ascent Lint brings greater ease-of-use and even faster turn-around time to the fast, high-capacity, low-noise lint analyzer. The updated debugger GUI allows editing of design source files, rule configurations, and inserting waivers from the violation line. Re-invoking lint analysis from the debugger GUI is dramatically faster with shorter turn-around times. Over 50 new SystemVerilog, Verilog, VHDL and netlist rules have been added.

The newest Meridian CDC furthers Real Intent's position in CDC analysis. It excels in speed, capacity and low noise analysis of asynchronous clock domains in SOC designs with a new formal engine which goes farther and faster to find hidden CDC problems. Design language support has been extended to include the SystemVerilog synthesizable subset. The user experience has been enhanced substantially in a new front-end interface which incorporates SpringSoft's Verdi Automated Debug System, and delivers improved analysis set-up, debug features and ease-of-use.

Demonstrations of the Ascent and Meridian products are set for June 4-6, 2012, at Real Intent's DAC booth #926.