May 31, 2012 -- Cortus SA has introduced the latest member of its processor family; the APS5. The APS5 combines good integer computational performance with a high maximum clock frequency. This processor IP is designed for ASICs requiring more complex processor subsystems such as those with instruction and data caches or co-processors. The APS5 can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with the APS3R.

The Cortus APS5 is a high-performance, high-throughput, 32-bit processor designed for complex embedded systems and features a high-performance integer unit and an instruction cache. It is the third member of the Cortus microcontroller IP core family to be released in 2012 complementing the smaller energy efficient APS3R and the larger floating-point FPS6.

"Despite its modest CPU core area, the APS5 delivers 2.29DMIPS/MHz," said Michael Chapman, CEO and President of Cortus. "In common with other Cortus processors, the APS5 has a 5- to 7-stage integer pipeline and out-of-order completion ensuring that most integer instructions (load and stores included) are executed in a single cycle. The APS5 architecture enables a high maximum clock frequency, for example it is capable of greater than 400 MHz in a 90 nm technology."

The APS5 has been designed to provide scalable computing performance and is supplied with an instruction cache and a data cache as optional. Performance can be increased with symmetric multi-processing (SMP) configurations such as dual- or quad-core. For example, while a single APS5 core offers 1.93CoreMarks/MHz, a dual-core configuration benchmarks at 3.51CoreMarks/MHz. For SMP configurations, a coherent data cache with snoopy protocol is available. Other applications may benefit from heterogeneous APS5/APS3R configurations.

The modest APS5 CPU core silicon footprint of 0.088 mm² in 90-nm (UMC) and the freely available complete toolchain and IDE ensure a very low cost of ownership for APS5 licensees. The easy software development, programming in high-level languages, with simple debugging due to an integrated debugger and simulator enhance both time-to-market and software reliability.

As a member of the Cortus family of processors, APS5 interfaces to all of Cortus peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. It also shares the simple vectored-interrupt structure which ensures rapid, real-time interrupt response, with low software overhead. Bridges to and from AHB-Lite and to APB ensure easy interfacing to other IP.

The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and which can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium µC/OS and µCLinux.