Page loading . . .

  
 Category: News: News Archive 2012: Tuesday, May 21, 2013
Breker Verification Systems Secures $5 Million in Funding  
 Printer friendly
 E-Mail Item URL

July 12, 2012 -- Breker Verification Systems, Inc. has raised $5 million in Series A funding. Funding was provided by Astor Capital Group, a private equity fund out of Far East Asia. Funds will be used as working capital to scale operations, expanding in all areas of sales, support and research and development.

Previously, Breker bootstrapped the company with a small, initial round of angel investment. That funding enabled Breker to gain market traction with TrekSoC, the first commercially available software that automates the generation of self-verifying test cases for multi-threaded system-on-chip (SOC) devices. TrekSoC is in production use at leading SOC design companies, including STMicroelectronics and NVIDIA.

Adnan Hamid, Breker Verification Systems' co-founder and CEO, said, "This round of funding demonstrates the strength of our technology and the unique value proposition that we bring to the SOC verification market. Our users have been excited with our solution, and we are extremely pleased to be in a position to scale our support and range of products."



Go to the Breker Verification Systems, Inc. website to find additional information.

Read more about
Breker Verification Systems, Inc.
on SOCcentral.com


Keywords: EDA, EDA tools, electronic design automation, ASICs, ASIC design, verification, Breker Verification Systems, TrekSoC,
601/38832 7/12/2012 359 64


Designer's Mall
0.4052734



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.601  0.4697266