July 24, 2012 -- Synopsys, Inc. today announced availability of the latest release of Synopsys' Virtualizer tool set for creating virtual prototypes and Virtualizer Development Kits (VDKs) that accelerate embedded-software development. The new Virtualizer release improves modeling productivity through its new model-authoring feature and IP specification import function, enabling engineers to develop system-level models and assemble them into virtual prototypes up to three times faster.In addition, enhanced support for popular debugger tools lets software developers easily integrate Virtualizer-based virtual prototypes into their existing software debug flows.
Synopsys' Virtualizer virtual-prototyping solution is an integral part a comprehensive solution of tools, models and services for early software development, hardware/ software integration, and system validation. Virtualizer addresses the increasing software complexity associated with semiconductor and electronic products by enabling the efficient creation of SystemC-based transaction-level models (TLMs), as well as the assembly of TLMs into virtual prototypes representing complete systems. The Virtualizer tool set is also used by designers to create customized VDKs, software-development kits containing design-specific virtual prototypes as well as debug and analysis tools and sample software, which can be deployed to software development teams up to 12 months before silicon availability. Ready-to-use VDKs for ARM big.LITTLE processing and ARM Cortex-A15 MPCore processor-based designs are also available from Synopsys.
This Virtualizer release incorporates a new graphical simulation profiler which makes it easier for virtual-prototyping teams to find and address simulation bottlenecks. Out-of-the-box support for the latest APIs in popular software debuggers such as Lauterbach TRACE32 System and ARM Development Studio 5 (DS-5) enables software teams to use VDKs to create a powerful, integrated environment for multicore software debug. In addition, integration with MathWorks' Simulink simulation environment enables more rapid deployment of virtual hardware-in-the-loop (HIL) testing.
The model-authoring interface in the new Virtualizer tool set simplifies and automates model creation with new features such as automatic design rule checking and design-sensitive help, improving modeling productivity for both virtual-prototyping experts as well as those less experienced. The new tool release also lets users import existing IP specifications in popular formats such as IP-XACT, Excel, Word and PDF, further speeding model development by automatically generating SystemC Modeling Library (SCML) constructs and industry-standard Accellera Systems Initiative TLM-2.0 bus interfaces.
In addition to providing improved model-creation capabilities, the most-recent Virtualizer release continues to support direct integration of TLM-2.0 standard-based models of common IP blocks readily available in the market, including Synopsys' DesignWare TLM Library models, ARM Fast Models, and other SystemC TLM models available from Synopsys. It also supports more than 900 system-level models that can be found on TLMCentral.
The new Virtualizer 12.06 release is available now.
Posted by: John Miklosz
Go to the Synopsys, Inc. website to find additional information.