July 30, 2012 -- Xilinx, Inc. has made available its first public release of its next-generation design environment. The Vivado Design Suite 2012.2 is now available at no additional cost to all ISE Design Suite users who are currently in warranty. This release is the first in a two-phase roll-out, with the first phase focused on accelerating time-to-implementation from C and RTL, and the second focused on accelerating time-to- integration of system-level functions.

Accelerates implementation from RTL

The Vivado Design Suite 2012.2 place-and-route technology accelerates implementation cycles by using analytical techniques to optimize for multiple and concurrent design metrics, such as congestion, total wire length and timing. For complex designs, this results in performance improvements of 15% corresponding to a 1-speed-grade advantage over the ISE Design Suite. The same performance improvement also extends Xilinx's high-performance leadership over competing devices by 3 speed grades among the mid-range families, while delivering better performance vs. power trade-offs on the high-end, and better performance on the low-cost end of the respective product portfolios.

Accelerates implementation from C

With the general release of the Vivado Design Suite, Xilinx provides Vivado High-Level Synthesis (HLS) for All Programmable 7 series FPGA and Zynq-7000 EPP SOC devices. Vivado HLS will be included at no additional cost to ISE Design Suite DSP Edition and System Edition users currently in warranty. Designers can quickly explore implementation architectures for complex algorithms by synthesizing their C, C++ or System C code to RTL. Vivado HLS also integrates with the System Generator tool by creating fast simulation models for enabling the rapid development of applications such as video, imaging, RADAR and baseband radios. Not only does Vivado HLS accelerate algorithm implementation, it also reduces verification time by up to 10,000X while improving system performance by enabling RTL micro-architecture exploration.

"In FPGA design, we always use C to quickly build a system-level model for validation of key algorithms and architectures, but we've always encountered the problem of how we could quickly and efficiently convert C into a hardware description language," said Hengqi Liu, Central R&D Data Center CTO at ZTE China. "With Xilinx Vivado High-Level Synthesis, this problem has been effectively addressed, as we recently used C to implement a key algorithm, and then used the tool to successfully map the C code into Verilog. We verified both the functionality and performance in Xilinx devices and the results showed that Vivado High-Level Synthesis is very useful in an FPGA design flow."

Integration and the Xilinx Alliance Program

To further accelerate designer productivity, Xilinx continues its on-going collaboration with its growing base of key Xilinx Alliance Program members by ensuring IP cores are validated and design tools are available to augment the ISE Design Suite and Vivado Design Suite tools. This collaboration is also key for the second phase of the Vivado Design Suite roll-out that includes the Vivado IP Integrator, an interactive design and verification environment, and the Vivado IP Packager, which enables Xilinx, third-party IP providers and end users to package a core, module or completed design with all constraints, testbenches and documentation.

Availability

In warranty ISE Design Suite Logic Edition and Embedded Edition users will receive the new Vivado Design Suite Edition, and those with ISE Design Suite DSP and System Edition will receive the new Vivado Design Suite System Edition at no additional cost.

The new features and methodologies for accelerating time-to-integration will be available early next year as part of the second phase of the Vivado Design Suite roll-out.

Posted by: John Miklosz