Page loading . . .

  
 Category: News: News Archive 2012: Saturday, May 18, 2013
DMP's PICA200 Lite 3D-Graphics IP Core adopted for Olympus Tough TG-1 Digital Camera  
 Printer friendly
 E-Mail Item URL

July 31, 2012 -- Digital Media Professionals, Inc. (DMP) today announced that its PICA200 Lite 3D-graphics IP core has been adopted for Olympus Tough TG-1 compact digital camera by Olympus Imaging Corp.

PICA200 Lite is a 3D-graphics IP core optimized for GUI (Graphical User Interface) applications and based on OpenGL ES1.1 specification. DMP claims that PICA200 Lite provides the industry's best performance vs. area vs. power consumption and the smallest silicon size. In the Olympus TG-1 it is used for visualizing "A-GPS" and "E.COMPASS" which provides new user experiences in compact cameras.

Posted by: John Miklosz



Go to the Digital Media Professionals, Inc. (DMP) website to find additional information.

E-mail Digital Media Professionals, Inc. (DMP) for more information.

Read more about
Digital Media Professionals, Inc. (DMP)
on SOCcentral.com


Keywords: ASICs, ASIC design, 3D graphics processors, graphics processing units, GPUs, PICA200 Lite 3D-Graphics IP, intellectual property, cores, Digital Media Professionals (DMP),
601/38905 7/31/2012 1209 85


Designer's Mall
0.390625



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.601  0.46875